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Section 8 I/O Ports
(5)
PA3/LLWR/LLB
The pin function is switched as shown below according to the combination of bus controller
register, and the PA3DDR bit settings.
Module Name
Pin Function
LLB output
Bus controller
LLWR output
(initial setting)
If the byte control SRAM space is accessed, this pin functions as the LLB output;
Note:
*
otherwise, the LLWR.
(6)
PA2/BREQ/WAIT
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, and the PA2DDR bit settings.
Module Name
Pin Function
BREQ input
Bus controller
WAIT input
I/O port
PA2 output
PA2 input
(initial setting)
Rev.2.00 Jun. 28, 2007 Page 278 of 666
REJ09B0311-0200
Bus Controller
LLB_OE*
1
Bus Controller
BCR_BRLE
1
0
0
0
Setting
I/O Port
LLWR_OE*
1
Setting
BCR_WAITE
1
0
0
PA3DDR
I/O Port
PA2DDR
1
0
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