Section 17 Clock Pulse Generator - Renesas H8SX/1650 Hardware Manual

This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (Iφ),
peripheral module clock (Pφ), and external bus clock (Bφ).
The clock pulse generator consists of an oscillator, PLL (Phase Locked Loop) circuit, divider, and
selector circuit. Figure 17.1 shows a block diagram of the clock pulse generator.
Clock frequencies can be changed by the PLL circuit and divider in the CPG. Changing the
system clock control register (SCKCR) setting by software can change the clock frequencies.
This LSI supports three types of clocks: a system clock provided to the CPU and bus masters, a
peripheral module clock provided to the peripheral modules, and an external bus clock provided to
the external bus. These clocks can be specified independently. Note, however, that the frequencies
of the peripheral clock and external bus clock are lower than that of the system clock.
EXTAL
Oscillator
XTAL
Figure 17.1 Block Diagram of Clock Pulse Generator

Section 17 Clock Pulse Generator

EXTAL × 4
PLL
circuit
EXTAL × 4
EXTAL × 2
EXTAL × 1
EXTAL × 1/2
Divider
(1/1,
1/2,
1/4,
and 1/8)
Rev.2.00 Jun. 28, 2007 Page 553 of 666
Section 17 Clock Pulse Generator
SCKCR
ICK2 to ICK0
Selector System clock (Iφ)
(to the CPU and
bus masters)
SCKCR
PCK2 to PCK0
1/1
1/2
Selector
Peripheral module
1/4
clock (Pφ)
1/8
(to peripheral modules)
SCKCR
BCK2 to BCK0
1/1
1/2
Selector External bus clock (Bφ)
1/4
(to the Bφ pin)
1/8
REJ09B0311-0200