Register Direct-Rn; Register Indirect-@Ern; Register Indirect With Displacement-@(D:2, Ern), @(D:16, Ern), Or @(D:32, Ern); Index Register Indirect With Displacement-@(D:16,Rnl.b), @(D:32,Rnl.b), @(D:16,Rn.w), @(D:32,Rn.w), @(D:16,Ern.l), Or @(D:32,Ern.l) - Renesas H8SX/1650 Hardware Manual

2.8.1 Register Direct—Rn
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the
register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit
registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified
as 32-bit registers.
2.8.2 Register Indirect—@ERn
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field in the instruction code.
In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are
valid and the upper eight bits are all assumed to be 0 (H'00).
2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or
@(d:32, ERn)
The operand value is the contents of a memory location which is pointed to by the sum of the
contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the
register field of the instruction code. The displacement is included in the instruction code and the
16-bit displacement is sign-extended when added to ERn.
This addressing mode has a short format (@(d:2, ERn)). The short format can be used: when a
displacement is 1, 2, or 3 and the operand is byte data, when a displacement is 2, 4, or 6 and the
operand is word data, or when a displacement is 4, 8, or 12 and the operand is longword data.
2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)
The operand value is the contents of a memory location which is pointed to by the sum of the
following operation result and a 16- or 32-bit displacement: specified bits of the contents of an
address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero-
extended to 32-bit data and multiplied by 1, 2, or 4.
The displacement is included in the instruction code and the 16-bit displacement is sign-extended
when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or
longword data, ERn is multiplied by 2 or 4, respectively.
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Section 2 CPU