Renesas H8SX/1650 Hardware Manual page 444

Section 11 8-Bit Timers (TMR)
• TCSR_0
Bit Bit Name
7 CMFB
6 CMFA
5 OVF
4 ADTE
Rev.2.00 Jun. 28, 2007 Page 422 of 666
REJ09B0311-0200
Initial
Value R/W Description
1
0 R/(W)* Compare Match Flag B
[Setting condition]
•
[Clearing conditions]
•
•
1
0 R/(W)* Compare Match Flag A
[Setting condition]
•
[Clearing conditions]
•
•
1
0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FF to H'00
[Clearing condition]
When writing 0 after reading OVF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
0 R/W A/D Trigger Enable
Selects enabling or disabling of A/D converter start
requests by compare match A.
0: A/D converter start requests by compare match A are
1: A/D converter start requests by compare match A are
When TCNT matches TCORB
When writing 0 after reading CMFB = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When the DTC is activated by a CMIB interrupt
while the DISEL bit in MRB of the DTC is 0
When TCNT matches TCORA
When writing 0 after reading CMFA = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When the DTC is activated by a CMIA interrupt
while the DISEL bit in MRB in the DTC is 0
disabled
enabled