Relation Between Writing To Tdr And Tdre Flag; Restrictions On Using Dtc - Renesas H8SX/1650 Hardware Manual

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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Section 13 Serial Communication Interface (SCI)
13.9.5

Relation between Writing to TDR and TDRE Flag

The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written
to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR
yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the
TDRE flag is set to 1.
13.9.6

Restrictions on Using DTC

• When the external clock source is used as a synchronization clock, update TDR by the DTC
and wait for at least five Pφ clock cycles before allowing the transmit clock to be input. If the
transmit clock is input within four clock cycles after TDR modification, the SCI may
malfunction (figure 13.33).
• When using the DTC to read RDR, be sure to set the receive end interrupt (RXI) as the DTC
activation source.
SCK
TDRE
Serial data
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 13.33 Sample Transmission using DTC in Clocked Synchronous Mode
Rev.2.00 Jun. 28, 2007 Page 520 of 666
REJ09B0311-0200
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7

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