Table of Contents
Advertisement
9.3.4
Timer Interrupt Enable Register (TIER)........................................................... 337
9.3.5
Timer Status Register (TSR)............................................................................. 339
9.3.6
Timer Counter (TCNT)..................................................................................... 343
9.3.7
Timer General Register (TGR) ......................................................................... 343
9.3.8
Timer Start Register (TSTR) ............................................................................ 344
9.3.9
Timer Synchronous Register (TSYR)............................................................... 345
9.4
Operation .......................................................................................................................... 346
9.4.1
Basic Functions................................................................................................. 346
9.4.2
Synchronous Operation..................................................................................... 352
9.4.3
Buffer Operation............................................................................................... 354
9.4.4
Cascaded Operation .......................................................................................... 357
9.4.5
PWM Modes..................................................................................................... 359
9.4.6
Phase Counting Mode....................................................................................... 364
9.5
Interrupt Sources............................................................................................................... 370
9.6
DTC Activation ................................................................................................................ 372
9.7
A/D Converter Activation................................................................................................. 372
9.8
Operation Timing.............................................................................................................. 373
9.8.1
Input/Output Timing ......................................................................................... 373
9.8.2
Interrupt Signal Timing .................................................................................... 377
9.9
Usage Notes ...................................................................................................................... 381
9.9.1
Module Stop State Setting ................................................................................ 381
9.9.2
Input Clock Restrictions ................................................................................... 381
9.9.3
Caution on Cycle Setting .................................................................................. 382
9.9.4
Conflict between TCNT Write and Clear Operations....................................... 382
9.9.5
Conflict between TCNT Write and Increment Operations ............................... 383
9.9.6
Conflict between TGR Write and Compare Match........................................... 383
9.9.7
Conflict between Buffer Register Write and Compare Match .......................... 384
9.9.8
Conflict between TGR Read and Input Capture ............................................... 384
9.9.9
Conflict between TGR Write and Input Capture .............................................. 385
9.9.10
Conflict between Buffer Register Write and Input Capture.............................. 386
9.9.11
Conflict between Overflow/Underflow and Counter Clearing ......................... 387
9.9.12
Conflict between TCNT Write and Overflow/Underflow ................................ 387
9.9.13
Multiplexing of I/O Pins ................................................................................... 388
9.9.14
Interrupts and Module Stop State ..................................................................... 388
Section 10 Programmable Pulse Generator (PPG)............................................ 389
10.1
Features............................................................................................................................. 389
10.2
Input/Output Pins.............................................................................................................. 391
10.3
Register Descriptions........................................................................................................ 392
10.3.1
Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 392
Rev.2.00 Jun. 28, 2007 Page xvi of xxii
Advertisement
Table of Contents
