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4.5.2
Address Error Exception Handling
When an address error occurs, address error exception handling starts after the bus cycle causing
the address error ends and current instruction execution completes. The address error exception
handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the address error is generated, the
start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Even though an address error occurs during a transition to an address error exception handling, the
address error is not accepted. This prevents an address error from occurring due to stacking for
exception handling, thereby preventing infinitive stacking.
If the SP contents are not a multiple of 2 when an address error exception handling occurs, the
stacked values (PC, CCR, and EXR) are undefined.
When an address error occurs, the following is performed to halt the DTC.
• The ERR bit in DTCCR is set to 1.
Table 4.6 shows the state of CCR and EXR after execution of the address error exception
handling.
Table 4.6
Status of CCR and EXR after Address Error Exception Handling
Interrupt Control Mode
0
2
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
CCR
I
UI
1
1
Section 4 Exception Handling
EXR
T
I2 to I0
0
7
Rev.2.00 Jun. 28, 2007 Page 77 of 666
REJ09B0311-0200
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