Renesas H8SX/1650 Hardware Manual page 215

Bφ
Address bus
CSn
AH
RD
Read
D15 to D0
LHWR
LLWR
Write
D15 to D0
BS
RD/WR
Note: n = 3 to 7
Figure 6.29 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1)
Bus cycle
Address cycle
T T
ma1 ma2
Address
Address
Section 6 Bus Controller (BSC)
Data cycle
T T
1 2
Read data
Write data
Rev.2.00 Jun. 28, 2007 Page 193 of 666
REJ09B0311-0200