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Section 9 16-Bit Timer Pulse Unit (TPU)
2. PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a cycle register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the
output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 9.31.
Table 9.31 PWM Output Registers and Output Pins
Channel
0
1
2
3
4
5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
Rev.2.00 Jun. 28, 2007 Page 360 of 666
REJ09B0311-0200
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
Output Pins
PWM Mode 1
TIOCA0
TIOCC0
TIOCA1
TIOCA2
TIOCA3
TIOCC3
TIOCA4
TIOCA5
PWM Mode 2
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
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