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Section 5 Interrupt Controller
5.4
Interrupt Sources
5.4.1
External Interrupts
There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to
leave software standby mode.
(1)
NMI Interrupts
Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by
the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on
the NMI pin.
When an NMI interrupt is generated, the interrupt controller determines that an error has occurred,
and performs the following procedure.
• Sets the ERR bit in DTCCR to 1.
(2)
IRQn Interrupts:
An IRQn interrupt is requested by a signal input on pins IRQ11 to IRQ0. IRQn (n = 11 to 0) have
the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, on pins IRQn.
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by
software. The bit manipulation instructions and memory operation instructions should be used
to clear the flag.
Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings,
and does not change regardless of the output setting. However, when a pin is used as an external
interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the
corresponding DDR bit to 0.
Rev.2.00 Jun. 28, 2007 Page 100 of 666
REJ09B0311-0200
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