Instructions And Addressing Modes - Renesas H8SX/1650 Hardware Manual

Section 2 CPU
2.7.1

Instructions and Addressing Modes

Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can
use.
Table 2.2 Combinations of Instructions and Addressing Modes (1)
Classifi-
cation Instruction
Data MOV
transfer
MOVFPE,
12
MOVTPE*
POP, PUSH
LDM, STM
4
MOVA*
Block EEPMOV
transfer
MOVMD
MOVSD
Arithmetic ADD, CMP
operations
SUB
ADDX, SUBX
INC, DEC
ADDS, SUBS
DAA, DAS
MULXU, DIVXU
MULU, DIVU
MULXS, DIVXS
Rev.2.00 Jun. 28, 2007 Page 34 of 666
REJ09B0311-0200
Size #xx Rn @ERn
B/W/L S SD SD
B S/D
B S/D
W/L S/D
L S/D
B/W S S
B
B/W/L
B
B/W/L S SD SD
B S D
B SD SD
W/L S SD SD
B/W/L S SD
B/W/L S SD
B/W/L S
B/W/L D
L D
B D
B/W S:4 SD
W/L S:4 SD
B/W S:4 SD
Addressing Mode
@(d, @−ERn/
RnL.B/ @ERn+/
Rn.W/ @ERn−/
@(d,ERn) ERn.L) @+ERn
SD SD SD
2
S/D*
2
S/D*
S S S
SD SD SD
D D D
SD SD SD
SD SD SD
5
SD*
@aa:16/

@aa:8 @aa:32
SD
S/D
1
S/D*
S
3
SD*
3
SD*
3
SD*
SD
D
SD
SD