Interrupt Sources; Usage Notes; Module Stop State Setting - Renesas H8SX/1650 Hardware Manual

located on the on-chip memory
7.8

Interrupt Sources

An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and priority level control in the interrupt controller.
7.9

Usage Notes

7.9.1

Module Stop State Setting

Operation of the DTC can be disabled or enabled using the module stop control register. The
initial setting is for operation of the DTC to be enabled. Register access is disabled by setting
module stop state. Module stop state cannot be set while the DTC is activated. For details, see
section 18, Power-Down States.
Transfer information
1st data transfer
Chain transfer
information
2nd data transfer
information
Figure 7.16 Chain Transfer when Counter = 0
Section 7 Data Transfer Controller (DTC)
Input circuit
Input buffer
(counter = 0)
Upper 8 bits of DAR
Rev.2.00 Jun. 28, 2007 Page 249 of 666
REJ09B0311-0200