Location Of Transfer Information And Dtc Vector Table - Renesas H8SX/1650 Hardware Manual

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
Table of Contents

Advertisement

Section 7 Data Transfer Controller (DTC)
7.4

Location of Transfer Information and DTC Vector Table

Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information can be located in either short address mode
(three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies
either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see
section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is
shown in figure 7.2.
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 7.3 shows
correspondences between the DTC vector address and transfer information.
Transfer information
in short address mode
Lower addresses
Start
address
0
1
MRA
MRB
Chain
transfer
CRA
MRA
MRB
CRA
4 bytes
Rev.2.00 Jun. 28, 2007 Page 228 of 666
REJ09B0311-0200
2
3
SAR
Transfer information
DAR
for one transfer
(3 longwords)
CRB
SAR
Transfer information
for the 2nd transfer
DAR
in chain transfer
(3 longwords)
CRB
Figure 7.2 Transfer Information on Data Area
Transfer information
in full address mode
Lower addresses
Start
0
1
2
address
Reserved
MRA MRB
(0 write)
SAR
DAR
Chain
transfer
CRA
CRB
Reserved
MRA MRB
(0 write)
SAR
DAR
CRA
CRB
4 bytes
3
Transfer
information
for one transfer
(4 longwords)
Transfer
information
for the 2nd
transfer
in chain transfer
(4 longwords)

Advertisement

Table of Contents
loading

This manual is also suitable for:

R5s61650cH8sx/1650c

Table of Contents