Renesas H8SX/1650 Hardware Manual page 57

Classifi-
cation Instruction
Arithmetic MULS, DIVS
operations
NEG
EXTU, EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Logic AND, OR, XOR
operations
NOT
Shift SHLL, SHLR
SHAL, SHAR
ROTL, ROTR
ROTXL, ROTXR B/W/L
Bit manipu- BSET, BCLR,
lation BNOT, BTST,
BSET/cc,
BCLR/cc
BAND, BIAND,
BOR, BIOR,
BXOR, BIXOR,
BLD, BILD,
BST, BIST,
BSTZ, BISTZ
BFLD
BFST
Branch BRA/BS,
8
BRA/BC*
BSR/BS,
8
BSR/BC*
Size #xx Rn @ERn
W/L S:4 SD
B/W/L D D
W/L D D
B D



S

D
B/W/L S SD SD
B/W/L D D
6
B/W/L* D D
7
B/W/L* D
B/W/L D D
B/W/L D D
D D
B D D
B D D
B D S
B S D
B S
B S
Addressing Mode
@(d, @−ERn/
RnL.B/ @ERn+/
Rn.W/ @ERn−/
@(d,ERn) ERn.L) @+ERn
D D D
D D D
SD SD SD
D D D
D D D
D D D
D D D
D D D
Rev.2.00 Jun. 28, 2007 Page 35 of 666
Section 2 CPU
@aa:16/

@aa:8 @aa:32
D
D
O
SD
D
D
D
D
D
D D
D D
S S
D D
S S
S S
REJ09B0311-0200