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USER'S MANUAL
S5PC100
June, 2009
REV 1.01
Copyright © 2009 Samsung Electronics, Inc. All Rights Reserved

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Summary of Contents for Samsung S5PC100

  • Page 1 USER'S MANUAL S5PC100 June, 2009 REV 1.01 Copyright © 2009 Samsung Electronics, Inc. All Rights Reserved...
  • Page 2: Important Notice

    Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
  • Page 3: Revision History

    Revision History Revision No. Description Author(s) Date 0.00 Initial Draft (Preliminary spec) AP design November, 2008 Following chapters are added - Electrical Data, Mechanical Data Following chapters are updated - Overview, Memory map, Chip ID, GPIO, Clock controller, Power management, Booting sequence, DRAM controller, SROM controller, OneNAND controller, NAND Flash controller, DMA controller, System timer, MIPI DSIM, MIPI CSIS, USB HOST...
  • Page 4: Product Overview

    PRODUCT OVERVIEW PRODUCT OVERVIEW 1 ARCHITECTURAL OVERVIEW S5PC100 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones and general applications, and integrates an ARM CortexTM-A8 which implements the ARM architecture V7-A with supporting numerous peripherals.
  • Page 5 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) 2 BLOCK DIAGRAM This section summarizes the features of the S5PC100. Figure 1.1- 1 shows an overall block diagram of the S5PC100. System Peripheral ARM Core Multimedia Acceleration CortexA8 Camera IF / CSI-2 PLL x 4...
  • Page 6 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW 3 FEATURES • ARM Cortex -A8 based CPU Subsystem with NEON ♦ 32/32KB I/D Cache, 256KB L2 Cache ♦ Operating frequency up to 667MHz at 1.2V. • 64-bit Multi-layer bus architecture ♦ D0_BUS domain for ARM Cortex -A8, Memory subsystem, Debugger, VIC, DMA, 2D, Security subsystem and CF controller, which shares pins with static memory controllers.
  • Page 7 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) • Configurable GPIOs • Real time clock, PLL, timer with PWM and watch dog timer. • System timer for variable tick. • Memory Subsystem ♦ SRAM/ROM/NOR/NAND Interface with x8 or x16 data bus ♦ Muxed OneNAND Interface with x16 data bus ♦...
  • Page 8 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW 3.2 MEMORY SUBSYSTEM • High bandwidth Memory Matrix subsystem • Two independent external memory ports (1 x16 Static Hybrid Memory port and 1 x32 DRAM port) • Matrix architecture increases overall bandwidth with the simultaneous access capability ♦...
  • Page 9 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) 3.3 MULTIMEDIA ACCELERATION • Camera Interface ♦ Multiple input support ITU-R BT 601/656 mode DMA (AXI 64bit interface) mode MIPI (CSI) mode ♦ Multiple output support DMA (AXI 64bit interface) mode Direct FIFO mode ♦...
  • Page 10 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW ♦ Supports error resilience tool in MPEG-4 decoding. ♦ Error detection and concealment in decoding. ♦ Up to quarter-pel search for H.264 ♦ Up to half-pel search for MPEG4 ♦ Motion estimation search range: [+/-64, +/-32] ♦...
  • Page 11 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) • 2D Graphic Accelerator ♦ Primitives: BitBlt and rotation, Color expansion, Line/Point Drawing ♦ Per-pixel Operations: 256 3-operand ROP, Alpha blending, Window clipping ♦ Data format: 16/24/32-bpp color format, YUV422 2plane ♦ 64-bit AXI interface •...
  • Page 12 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW ♦ Support overlapping & blending input video & graphic layers ♦ Support 480i/p, 576i/p, 720p and 1080i display size ♦ Support 4 layers (1 video layer, 2 graphic layer, 1 background layer) 3.4 AUDIO SUBSYSTEM •...
  • Page 13 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) ♦ 16-level alpha blending ♦ ITU-BT601/656 format output 1.1-10...
  • Page 14 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW 3.7 CONNECTIVITY • PCM Audio Interface ♦ 16-bit mono audio I/F ♦ Master mode only ♦ Support 2 port PCM interface • AC97 Audio Interface ♦ Independent channels for stereo PCM In, stereo PCM Out, mono MIC In.
  • Page 15 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) ♦ High speed synchronous serial interface • CompactFlash Controller ♦ Supports Compact Flash Specification Revision 3.0 ♦ Compatible with the ATA/ATAPI-6 standard • IrDA ♦ Dedicated IrDA for v1.1 (1.152Mpbs and 4Mpbs) ♦ SIR(111.5kbps) mode is supported by the URAT IrDA 1.0 block ♦...
  • Page 16 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW • HS-MMC/SDIO Interface ♦ Multimedia Card Protocol version 4.0 compatible (HS-MMC) ♦ SD Memory Card Protocol version 2.0 compatible ♦ DMA based or Interrupt based operation ♦ 128 word FIFO for Tx/Rx ♦ 3-channel HS-MMC or 3-channel SDIO •...
  • Page 17 PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0) 3.8 SYSTEM PERIPHERAL • Real Time Clock ♦ Full clock features: sec, min, hour, date, day, month, year ♦ 32.768kHz operation ♦ Alarm interrupt ♦ Time-tick interrupt • ♦ Four on-chip PLLs, APLL/MPLL/EPLL/HPLL ♦ APLL dedicates to ARM core ♦...
  • Page 18 S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW • A/D Converter and Touch Screen Interface ♦ 10-ch multiplexed ADC ♦ Max. 500Ksamples/sec and 12-bit resolution • Watch Dog Timer ♦ 16-bit watch dog timer • Vectored Interrupt Controller ♦ Multiple interrupt request inputs, one for each interrupt source, and one interrupt request output for the processor interrupt request input ♦...
  • Page 19 833MHz@ ARM1.33V/Internal 1.25V NOTES: 1.S5PC100 has three system clock domains called D0, D1 and D2. D0 domain is for CPU system, while D1 for multimedia, D2 for low power audio. Nominal 133/166MHz represents that D1 system frequency is 133MHz & D0 system frequency is 166MHz at 1.2V power level.
  • Page 20: Table Of Contents

    S5PC100 USER’S MANUAL (REV1.0) MEMORY MAP MEMORY MAP 1 MEMORY ADDRESS MAP Start Addr Limit Addr Size Usage Note Mirrored Region of 0xD000_0000~ 0x0000_0000 0x0008_0000 32KB IROM 0xD800_0000 0x0002_0000 0x0003_8000 96KB IRAM 0x2000_0000 0x6000_0000 DRAM 0x8000_0000 0x8800_0000 128MB SMC Bank 0...
  • Page 21 MEMORY MAP S5PC100 USER’S MANUAL (REV1.0) 1.2-2...
  • Page 22 S5PC100 USER’S MANUAL (REV1.0) MEMORY MAP 2 SPECIAL FUNCTION REGISTER MAP 0xE1F0_0000 0xE3F0_0000 0xE5F0_0000 0xE1E0_0000 0xE3E0_0000 0xE5E0_0000 0xE1D0_0000 0xE3D0_0000 0xE5D0_0000 0xE1C0_0000 0xE3C0_0000 0xE5C0_0000 0xE1B0_0000 0xE3B0_0000 0xE5B0_0000 0xE1A0_0000 0xE3A0_0000 0xE5A0_0000 0xE190_0000 0xE390_0000 0xE590_0000 0xE180_0000 TZPC0 0xE380_0000 0xE580_0000 0xE170_0000 0xE370_0000 0xE570_0000 0xE160_0000...
  • Page 23 MEMORY MAP S5PC100 USER’S MANUAL (REV1.0) 0xE7F0_0000 0xE9F0_0000 0xEBF0_0000 0xE7E0_0000 0xE9E0_0000 0xEBE0_0000 0xE7D0_0000 0xE9D0_0000 0xEBD0_0000 0xE7C0_0000 0xE9C0_0000 0xEBC0_0000 0xE7B0_0000 0xE9B0_0000 0xEBB0_0000 0xE7A0_0000 0xE9A0_0000 0xEBA0_0000 0xE790_0000 0xE990_0000 0xEB90_0000 CF controller 0xE780_0000 0xE980_0000 0xEB80_0000 0xE770_0000 0xE970_0000 0xEB70_0000 0xE760_0000 0xE960_0000 0xEB60_0000 0xE750_0000 0xE950_0000...
  • Page 24 S5PC100 USER’S MANUAL (REV1.0) MEMORY MAP 0xEDF0_0000 0xEFF0_0000 0xF1F0_0000 0xEDE0_0000 0xEFE0_0000 0xF1E0_0000 0xEDD0_0000 0xEFD0_0000 0xF1D0_0000 0xEDC0_0000 0xEFC0_0000 0xF1C0_0000 0xEDB0_0000 0xEFB0_0000 0xF1B0_0000 HS_SD/MMC2 0xEDA0_0000 0xEFA0_0000 0xF1A0_0000 HS_SD/MMC1 0xED90_0000 0xEF90_0000 0xF190_0000 HS_SD/MMC0 0xED80_0000 0xEF80_0000 0xF180_0000 0xED70_0000 0xEF70_0000 0xF170_0000 0xED60_0000 0xEF60_0000 0xF160_0000 Modem interface...
  • Page 25 MEMORY MAP S5PC100 USER’S MANUAL (REV1.0) 0xF3F0_0000 0xF5F0_0000 0xF7F0_0000 0xF3E0_0000 0xF5E0_0000 0xF7E0_0000 0xF3D0_0000 0xF5D0_0000 0xF7D0_0000 0xF3C0_0000 0xF5C0_0000 0xF7C0_0000 0xF3B0_0000 0xF5B0_0000 0xF7B0_0000 0xF3A0_0000 0xF5A0_0000 0xF7A0_0000 0xF390_0000 0xF590_0000 0xF790_0000 Cellguide 0xF380_0000 0xF580_0000 0xF780_0000 0xF370_0000 0xF570_0000 0xF770_0000 0xF360_0000 0xF560_0000 0xF760_0000 0xF350_0000 0xF550_0000 0xF750_0000...
  • Page 26 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (POP) BALL MAP & SIZE 1 PIN ASSIGNMENT 1.1 PIN ASSIGNMENT DIAGRAM - 580-BALL FCFBGA (POP) Figure 1.3- 1 S5PC100 Pin Assignment (580-FCFBGA) Bottom View 1.1-1...
  • Page 27 BALL MAP & SIZE (POP) S5PC100 USER’S MANUAL (REV1.0) 1.2 PIN NUMBER ORDER Table 1.3-1 S5PC100 580 FCFBGA Pin Assignment − Pin Number Order (1/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name Xm0ADDR[4] C27 XpwmTOUT[2]...
  • Page 28 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (POP) Table 1.1-2 S5PC100 580 FCFBGA Pin Assignment − Pin Number Order (2/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XvVD[18] XciDATA[7] XvVCLK VCCQ_O XefFSOURCE_0 XvVD[12] XciDATA[6]...
  • Page 29 BALL MAP & SIZE (POP) S5PC100 USER’S MANUAL (REV1.0) Table 1.1-3 S5PC100 580 FCFBGA Pin Assignment − Pin Number Order (3/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name Xi2s1LRCK XEINT[13] VDDQ_A AA16 VDD_EPLL Xi2s1CDCLK XEINT[12]...
  • Page 30 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (POP) Table 1.1-4 S5PC100 580 FCFBGA Pin Assignment − Pin Number Order (4/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XmsmCSn AE18 POP_ADDR[10] AF27 VDD12_HDMI AE19 POP_BA[1]...
  • Page 31 BALL MAP & SIZE (POP) S5PC100 USER’S MANUAL (REV1.0) 1.3 POWER AND GROUND PIN ASSIGNMENT TABLE 1.1-5 S5PC100 POWER PIN TO BALL ASSIGNMENT Power Pin Name Ball Description Group R26, R27, W27, AC26, AD11, AD13, AE7, VDDQ_A OneDRAM A port I/O...
  • Page 32 AA16 EPLL VDD_HPLL AD12 HPLL VDD33_UOTG USB OTG Phy VDD12_UOTG AE20 USB OTG Phy VDD33_ADC AB25 Table 1.1-6 S5PC100 Ground Pin to Ball Assignment Power Pin Name Ball Group VSSQ_DDR VSSQ_M0 VSSQ_LCD VSSQ_CI VSSQ_MMC VSSQ_AUD VSSQ_MSM A1, A2, A26, A27, B1, B2, B26, B27, C3, C9, C15, C21, C25, D9, D15, F14,...
  • Page 33 BALL MAP & SIZE (POP) S5PC100 USER’S MANUAL (REV1.0) VSS_HPLL AA12 VSSQ_UOTG AA19 VSS_UOTG AF21 VSS_ADC 1.1-8...
  • Page 34 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (POP) MCP CONNECTION 1.1-9...
  • Page 35 BALL MAP & SIZE (POP) S5PC100 USER’S MANUAL (REV1.0) PACKAGE DIMENSION Figure 12.2- 1 S5PC100 Package Dimension (580-FCFBGA)- Top View 1.1-10...
  • Page 36 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (POP) Figure 12.2- 2 S5PC100 Package Dimension (580-FCFBGA) − Side View 1.1-11...
  • Page 37 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (SingleChip) BALL MAP & SIZE 1 PIN ASSIGNMENT 1.1 PIN ASSIGNMENT DIAGRAM - 521-BALL FCFBGA (SINGLE CHIP) Figure 1.3 - 1 S5PC100 Pin Assignment (521-FCFBGA) Bottom View 1.1-1...
  • Page 38 BALL MAP & SIZE (SingleChip) S5PC100 USER’S MANUAL (REV1.0) 1.2 PIN NUMBER ORDER Table 1.3-1 S5PC100 521 FCFBGA Pin Assignment − Pin Number Order (1/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name Xm1DATA[16] Xm1DATA[4] Xm1ADDR[12]...
  • Page 39 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (SingleChip) Table 1.3-2 S5PC100 521 FCFBGA Pin Assignment − Pin Number Order (2/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name Xm0FCLE XciRESET VDD_INT Xm0FWEn Xm0ADDR[3] XEINT[7] Xm0FREn...
  • Page 40 BALL MAP & SIZE (SingleChip) S5PC100 USER’S MANUAL (REV1.0) Table 1.3-3 S5PC100 521 FCFBGA Pin Assignment − Pin Number Order (3/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XnRSTOUT XEINT[28] AA15 XEINT[23] XdacCOMP XOM[0] AA16...
  • Page 41 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (SingleChip) Table 1.1-4 S5PC100 521 FCFBGA Pin Assignment − Pin Number Order (4/4) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name AF14 VDD18_MIPI AG17 XmipiTXCN AF15 XmipiDN[1] XdacOUT[1]...
  • Page 42 BALL MAP & SIZE (SingleChip) S5PC100 USER’S MANUAL (REV1.0) 1.3 POWER PINS Table 1.1-5 S5PC100 Power Pin to Ball Assignment (1/2) Power Group Pin Name Ball Description VDDQ_DDR C16, C21, D20, H15, J11 DRAM I/O VDDQ_M0 B9, E3, K3 Memory(EBI) I/O...
  • Page 43 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (SingleChip) Table 1.1-6 S5PC100 Power Pin to Ball Assignment (2/2) Power Group Pin Name Ball VSSQ_DDR VSSQ_M0 VSSQ_LCD VSSQ_CI VSSQ_MMC VSSQ_AUD VSSQ_MSM Digital I/O VSSQ_SYS0 A1, A2, A26, A27, AD10, AD20, AF1, AF27, AG1, AG2, AG26, AG27, B1,...
  • Page 44 BALL MAP & SIZE (SingleChip) S5PC100 USER’S MANUAL (REV1.0) PACKAGE DIMENSION Figure 1.3- 1 S5PC100 Package Dimension (521-FCFBGA) − Top View 1.1-8...
  • Page 45 S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (SingleChip) Figure 1.3- 2 S5PC100 Package Dimension (521-FCFBGA) − Side View 1.1-9...
  • Page 46 If there are more than one instance of the controller of the booting device, only the first instance of the controller is used for booting. S5PC100 has 32KB ROM (iROM) and 96KB SRAM (iRAM) inside the chip. At the system reset, the program execution starts at iROM.
  • Page 47 IROM CODE S5PC100 USER’S MANUAL (REV1.0) The boot loader is divided into the BL0(1st boot loader) and the BL1(2nd boot loader). • BL0 which is placed in iROM loads BL1 from the booting device to iRAM. The booting device is determined by the OM and NFMOD pins.
  • Page 48 S5PC100 USER’S MANUAL (REV1.0) IROM CODE down modes. Because the system is entered into ESLEEP mode on the emergency case such as battery fault, there is no safe memory space on the whole system. So, any status information will not be saved to DRAM before entering ESLEEP mode.
  • Page 49 IROM CODE S5PC100 USER’S MANUAL (REV1.0) 12 Mhz 300.0 Mhz 100.0 Mhz 79.5 Mhz 20.6 Mhz 2.6-4...
  • Page 50 S5PC100 USER’S MANUAL (REV1.0) IROM CODE If there occurs an error in BL0, BL0 writes the error code at the Inform register (0xE010841C) and go to the USB booting. The error codes are as follows. Error Code Description OM[2:1] is not 0x0(NAND), 0x1(OneNAND), 0x2(MoviNAND)
  • Page 51 IROM CODE S5PC100 USER’S MANUAL (REV1.0) 3 I/O DESCRIPTION Function Description Type Signal OM[4]: 0 = normal mode, 1 = test mode OM[3]: 0 = 1st boot loader in iROM , 1 = reserved OM[2:1] : 00 = 2nd boot loader in NAND flash...
  • Page 52: X0000

    0x0003???? 4.1 PRODUCT ID REGISTER (PRO_ID, R, ADDRESS = 0XE000_0000) Field Description Reset Value Product ID [31:12] Product ID 0x43100 The product ID allocated to S5PC100 is “0x43100” Reserved [11:10] Should be zero Package mode [9:8] Package mode Device dependent 2’0X : discrete...
  • Page 53 PAD CONTROL PAD CONTROL 1 OVERVIEW S5PC100 includes 203 multi-functional input/ output pins and 108 memory pins. There are 29 general groups and 2 memory groups as listed below: • GPA0: 8 in/out pin – 2xUART with flow control • GPA1: 5 in/out pin – 2xUART without flow control or 1xUART with flow control, 1x IrDA •...
  • Page 54 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 3 DRIVE STRENGTH Output driver are subdivided into Type A, Type B, Type OSC_A and Type OSC_B. 3.1 OUTPUT DRIVER TYPES Driver Types GPA0, GPA1, GPB, GPC, GPD, GPE0, GPE1, GPF0, GPF1, GPF2, GPF3, GPG0,...
  • Page 55 S5PC100 USER’S MANUAL (REV1.0) PAD CONTROL 3.3 DC CURRENTS OF OUTPUT DRIVER TYPE A, B, OSC_A AND OSC_B ( VDD=2.5V±0.2V) VDD=2.30V VDD=2.50V VDD=2.70V Driver Type T=125℃ T=25℃ T=-40℃ 1.4mA 2.2mA 3.1mA 2.8mA 4.4mA 6.2mA 4.2mA 6.6mA 9.3mA 5.7mA 8.9mA 12.4mA 2.8mA...
  • Page 56 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 3.4 DC CURRENTS OF OUTPUT DRIVER TYPE A, B, OSC_A AND OSC_B ( VDD=1.8V±0.15V) VDD=1.65V VDD=1.80V VDD=1.95V Driver Type T=125℃ T=25℃ T=-40℃ 1.1mA 1.6mA 2.4mA 2.0mA 3.3mA 4.8mA 3.0mA 4.9mA 7.3mA 4.0mA 6.6mA 9.7mA 2.0mA...
  • Page 57 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 4 I/O DESCRIPTION GPIO consists of two part, alive-part and off-part. In Alive-part power is supplied on sleep mode, but in off-part it is not the same. Therefore, the registers in alive-part keep their values during sleep mode.
  • Page 58 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 4.1 PIN SUMMARY Type Function Description Control at power down mode is possible, power down mode is release by IO_RET_RELEASE[31] Control at power down mode is possible, power down mode is released automatically Alive I/O On power-down, they are set to be input without pull-up/down.
  • Page 59 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Pad Name Function Singnals Pull XpwmTOUT[0] GPD[0] / TOUT0 / PWM_TCLK VDDQ_EXT XpwmTOUT[1] GPD[1] / TOUT1 / EX_DMA_REQn VDDQ_EXT XpwmTOUT[2] GPD[2] / TOUT2 / EX_DMA_ACKn VDDQ_EXT XI2C0SDA GPD[3] / I2C0_SDA VDDQ_EXT XI2C0SCL GPD[4] / I2C0_SCL...
  • Page 60 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Pad Name Function Singnals Pull XvVD[11] GPF1[7] / LCD_VD[11] / SYS_VD[11] / V656_D[3] VDDQ_LCD XvVD[12] GPF2[0] / LCD_VD[12] / SYS_VD[12] / V656_D[4] VDDQ_LCD XvVD[13] GPF2[1] / LCD_VD[13] / SYS_VD[13] / V656_D[5] VDDQ_LCD XvVD[14] GPF2[2]...
  • Page 61 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Pad Name Function Singnals Pull Xmmc2DATA[3] GPG3[5] / SD2_D[3] / SPDIF_OUT VDDQ_MMC Xmmc2CDn GPG3[6] / SD2_CDn / SPDIF_EXTCLK VDDQ_MMC XEINT[0] GPH0[0] / WKUP_INT[0] VDDQ_SYS0 XEINT[1] GPH0[1] / WKUP_INT[1] VDDQ_SYS0 XEINT[2] GPH0[2] / WKUP_INT[2] VDDQ_SYS0...
  • Page 62 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Pad Name Function Singnals Pull XNFMOD[0] GPI[2] / NFMOD[0] VDDQ_SYS0 XNFMOD[1] GPI[3] / NFMOD[1] VDDQ_SYS0 XNFMOD[2] GPI[4] / NFMOD[2] VDDQ_SYS2 XNFMOD[3] GPI[5] / NFMOD[3] VDDQ_SYS2 XNFMOD[4] GPI[6] / NFMOD[4] VDDQ_SYS2 XNFMOD[5] GPI[7] / NFMOD[5]...
  • Page 63 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Pad Name Function Singnals Pull XmsmWEn GPJ4[1] / MSM_WEn / CF_nCS[1] VDDQ_MSM XmsmRn GPJ4[2] / MSM_REn / CF_IORDn VDDQ_MSM XmsmIRQn GPJ4[3] / MSM_IRQn / CF_IOWRn VDDQ_MSM Xm0CSn[0] GPK0[0] / SMC_nCS[0] VDDQ_M0 Xm0CSn[1] GPK0[1] / SMC_nCS[1]...
  • Page 64 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Pad Name Function Singnals Pull Xm0ADDR[3] GPL0[3] / EBI_A[3] VDDQ_M0 Xm0ADDR[4] GPL0[4] / EBI_A[4] VDDQ_M0 Xm0ADDR[5] GPL0[5] / EBI_A[5] VDDQ_M0 Xm0ADDR[6] GPL0[6] / EBI_A[6] VDDQ_M0 Xm0ADDR[7] GPL0[7] / EBI_A[7] VDDQ_M0 Xm0ADDR[8] GPL1[0] / EBI_A[8]...
  • Page 65 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Pad Name Function Singnals Pull XDDR2_SEL DDR2SEL VDDQ_EXT XjTRSTn TRSTn VDDQ_EXT XjTMS VDDQ_EXT XjTCK VDDQ_EXT XjTDO VDDQ_EXT XjTDI VDDQ_EXT XjDBGSEL DBGSEL VDDQ_EXT XuhDP UHOST_DP VDD_UH XuhDN UHOST_DN VDD_UH XPWRRGTON PWRRGTON VDDQ_SYS0 XnRESET nRESET VDDQ_SYS0...
  • Page 66 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Pad Name Function Singnals Pull XadcAIN[1] ADC_IN[1] VDD_ADC XadcAIN[0] ADC_IN[0] VDD_ADC XadcVref ADC_VREF VDD_ADC XusbDRVVBUS USB_DRVVBUS VDDQ_USB XusbDM USB_DM VDDQ_USB XusbREXT USB_REXT VDDQ_USB XusbDP USB_DP VDDQ_USB XusbVBUS USB_VBUS VDDQ_USB XusbID USB_ID VDDQ_USB XmipiDP[5] MIPI_DP[5]...
  • Page 67 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Pad Name Function Singnals Pull XdacOUT[2] DAC_OUT[2] VDDQ_MSM XdacIREF DAC_IREF VDDQ_MSM XdacVREF DAC_VREF VDDQ_MSM XdacCOMP DAC_COMP VDDQ_MSM XdacOUT[0] DAC_OUT[0] VDDQ_MSM XI2S0LRCK I2S0_LRCK VDDQ_AUD XI2S0CDCLK I2S0_CDCLK VDDQ_AUD XI2S0SCLK I2S0_SCLK VDDQ_AUD XI2S0SDI I2S 0_SDI VDDQ_AUD XI2S0SDO[0]...
  • Page 68 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Pad Name Function Singnals Pull Xm1WEn DDR_WEn VDDQ_DDR Xm1DATA[0] DDR_D[0] VDDQ_DDR Xm1DATA[1] DDR_D[1] VDDQ_DDR Xm1DATA[2] DDR_D[2] VDDQ_DDR Xm1DATA[3] DDR_D[3] VDDQ_DDR Xm1DATA[4] DDR_D[4] VDDQ_DDR Xm1DATA[5] DDR_D[5] VDDQ_DDR Xm1DATA[6] DDR_D[6] VDDQ_DDR Xm1DATA[7] DDR_D[7] VDDQ_DDR Xm1DATA[8] DDR_D[8]...
  • Page 69 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Pad Name Function Singnals Pull Xm1DATAQM[3] DDR_DQM[3] VDDQ_DDR Xm1DATAQS[0] DDR_DQS[0] VDDQ_DDR Xm1DATAQS[1] DDR_DQS[1] VDDQ_DDR Xm1DATAQS[2] DDR_DQS[2] VDDQ_DDR Xm1DATAQS[3] DDR_DQS[3] VDDQ_DDR Xm1DATAQSn[0] DDR_DQSn[0] VDDQ_DDR Xm1DATAQSn[1] DDR_DQSn[1] VDDQ_DDR Xm1DATAQSn[2] DDR_DQSn[2] VDDQ_DDR Xm1DATAQSn[3] DDR_DQSn[3] VDDQ_DDR 2.2-17...
  • Page 70 GPxCON, GPxDAT, GPxPULL, GPxDRV work in normal mode, GPxPDNCON, GPxPDNPULL work in power down mode(DEEP-IDLE and Top-off, DEEP-STOP and Top-off, SLEEP mode). If, S5PC100 enter the power down mode, all configurations and Pull-down controls are selected by power down registers...
  • Page 71 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Register Address Description Reset Value GPDDAT 0xE030_0084 Port Group GPD Data Register GPDPULL 0xE030_0088 Port Group GPD Pull-up/down Register 0x1555 GPDDRV 0xE030_008C Port Group GPD Drive strength control Register 0x0000 Port Group GPD Power down mode Configuration...
  • Page 72 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value GPF2CON 0xE030_0120 Port Group GPF2 Configuration Register 0x00000000 GPF2DAT 0xE030_0124 Port Group GPF2 Data Register GPF2PULL 0xE030_0128 Port Group GPF2 Pull-up/down Register 0x5555 GPF2DRV 0xE030_012C Port Group GPF2 Drive strength control Register...
  • Page 73 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Register Address Description Reset Value up/down Register GPG3CON 0xE030_01C0 Port Group GPG3 Configuration Register 0x00000000 GPG3DAT 0xE030_01C4 Port Group GPG3 Data Register GPG3PUD 0xE030_01C8 Port Group GPG3 Pull-up/down Register 0x1555 GPG3DRV 0xE030_01CC Port Group GPG3 Drive strength control Register...
  • Page 74 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value Port Group GPJ0 Power down mode GPJ0PDNCON 0xE030_0210 0x00 Configuration Register Port Group GPJ0 Power down mode Pull-up/down GPJ0PDNPULL 0xE030_0214 0x00 Register GPJ1CON 0xE030_0220 Port Group GPJ1 Configuration Register...
  • Page 75 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Register Address Description Reset Value GPK0DRV 0xE030_02AC Port Group GPK0 Drive strength control Register 0xAAAA Port Group GPK0 Power down mode GPK0PDNCON 0xE030_02B0 0x00 Configuration Register Port Group GPK0 Power down mode Pull- GPK0PDNPULL...
  • Page 76 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value GPL1PULL 0xE030_0348 Port Group GPL1 Pull-up/down Register 0x0000 GPL1DRV 0xE030_034C Port Group GPL1 Drive strength control Register 0xAAAA Port Group GPL1 Power down mode GPL1PDNCON 0xE030_0350 0x00 Configuration Register...
  • Page 77 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Register Address Description Reset Value ETC0PULL 0xE030_04E8 Port Group ETC0 Pull-up/down Register 0x04AA ETC0DRV 0xE030_04EC Port Group ETC0 Drive strength control Register 0x0000 ETC1PULL 0xE030_0508 Port Group ETC1 Pull-up/down Register 0x8555 ETC1DRV 0xE030_050C Port Group ETC1 Drive strength control Register...
  • Page 78 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Reset Register Address Description Value NWU_INT1_FLTCON1 0xE030_080C Non wake-up Interrupt 1 Filter Configuration Register 1 NWU_INT2_FLTCON0 0xE030_0810 Non wake-up Interrupt 2 filter configuration register 0 NWU_INT3_FLTCON1 0xE030_0814 Non wake-up Interrupt 2 filter configuration register 1...
  • Page 79 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Reset Register Address Description Value NWU_INT0_MASK 0xE030_0900 Non wake-up Interrupt 0 Mask Register 0xff NWU_INT1_MASK 0xE030_0904 Non wake-up Interrupt 1 Mask Register 0x1f NWU_INT2_MASK 0xE030_0908 Non wake-up Interrupt 2 Mask Register 0xff NWU_INT3_MASK 0xE030_090C...
  • Page 80 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Reset Register Address Description Value NWU_INT15_PEND 0xE030_0A3C Non wake-up Interrupt 15 Pending Register NWU_INT16_PEND 0xE030_0A40 Non wake-up Interrupt 16 Pending Register NWU_INT17_PEND 0xE030_0A44 Non wake-up Interrupt 17 Pending Register NWU_INT18_PEND 0xE030_0A48 Non wake-up Interrupt 18 Pending Register...
  • Page 81 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Register Address Description Reset Value UHOST 0xE030_0B68 USB Host 1.1 Pad Configure Register Reset Register Address Description Value WKUP_INT_CON0_7 0xE030_0E00 Wake-up Interrupt Configuration Register0_7 WKUP_INT_CON8_15 0xE030_0E04 Wake-up Interrupt Configuration Register8_15 WKUP_INT_CON16_23 0xE030_0E08 Wake-up Interrupt Configuration Register16_23...
  • Page 82 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.1 PORT CONFIGURATION REGISTERS 5.1.1 Port Group GPA0 Configuration Register (GPA0CON, R/W, Address = 0xE030_0000) Field Description Reset Value 0000 = Input, 0001 = Output, 0010 = UART_0_RXD, GPA0CON[0] [3:0] 0000 1111 = NWU_INT0[0]...
  • Page 83 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 0000 = Input, 0001 = Output, 0010 = SPI_0_MOSI, GPBCON[2] [11:8] 0000 1111 = NWU_INT2[2] 0000 = Input, 0001 = Output, 0010 = SPI_0_nSS, GPBCON[3] [15:12] 0000 1111 = NWU_INT2[3] 0000 = Input, 0001 = Output, 0010 = SPI_1_MISO,...
  • Page 84 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 0000 = Input, 0001 = Output, 0010 = I2C1_SDA , GPDCON[5] [23:20] 0000 0011 = SPDIF_0_OUT, 1111 = NWU_INT4[5] 0000 = Input, 0001 = Output, 0010 = I2C1_SCL, GPDCON[6] [27:24] 0000 0011 = SPDIF_EXTCLK, 1111 = NWU_INT4[6] 5.1.6 Port Group GPE0 Configuration Register (GPE0CON, R/W, Address = 0xE030_00A0)
  • Page 85 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.1.8 Port Group GPF0 Configuration Register (GPF0CON, R/W, Address = 0xE030_00E0) Field Description Reset Value 0000 = Input, 0001 = Output, 0010 = LCD_HSYNC, GPF0CON[0] [3:0] 0011 = SYS_CS0, 0100 = VEN_HSYNC 0000 1111 = NWU_INT7[0]...
  • Page 86 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 0000 = Input, 0001 = Output, 0010 = LCD_VD[9], GPF1CON[5] [23:20] 0011 = SYS_VD[9], 0100 = V656_D[1], 0000 1111 = NWU_INT8[5] 0000 = Input, 0001 = Output, 0010 = LCD_VD[10], GPF1CON[6] [27:24] 0011 = SYS_VD[10], 0100 = V656_D[2],...
  • Page 87 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 1111 = NWU_INT10[2] 0000 = Input, 0001 = Output, 0010 = LCD_VD[23], GPF3CON[3] [15:12] 0011 = SYS_OE, 0100 = VEN_FIELD, 0000 1111 = NWU_INT10[3] 5.1.12 Port Group GPG0 Configuration Register (GPG0CON, R/W, Address = 0xE030_0160)
  • Page 88 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 0000 = Input, 0001 = Output, 0010 = SD_1_D[1], GPG2CON[3] [15:12] 0000 1111 = NWU_INT13[3] 0000 = Input, 0001 = Output, 0010 = SD_1_D[2], GPG2CON[4] [19:16] 0000 1111 = NWU_INT13[4] 0000 = Input, 0001 = Output, 0010 = SD_1_D[3],...
  • Page 89 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL GPH0CON[0] [3:0] 0000 = Input, 0001 = Output, 0010 = WKUP_INT[0] 0000 NOTE: WKUP_INT[x] are used for wake-up source in Power down and Idle mode, in Normal mode,these are same as NWU_INTx 5.1.17 Port Group GPH1 Configuration Register (GPH1CON, R/W, Address = 0xE030_0C20)
  • Page 90 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 0000 = Input, 0001 = Output, 0010 = WAKEUP_INT[16] , GPH2CON[0] [3:0] 0000 0011 = KEYPAD_COL[0], 0100 = CAM_B_D[0] Note: WAKEUP_INT[x] are used for wake-up source in Power down and Idle mode, in Normal mode, these are same as NWU_INTx 5.1.19...
  • Page 91 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 1111 = NWU_INT15[6] 0000 = Input, 0001 = Output, 0010 = BOOT_OPT[5], GPICON[7] [31:28] 1111 = NWU_INT15[7] 5.1.21 Port Group GPJ0 Configuration Register (GPJ0CON, R/W, Address = 0xE030_0200) Field Description Reset Value 0000 = Input, 0001 = Output, 0010 = MSM_A[0],...
  • Page 92 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.1.23 Port Group GPJ2 Configuration Register (GPJ2CON, R/W, Address = 0xE030_0240) Field Description Reset Value 0000 = Input, 0001 = Output, 0010 = MSM_D[0], GPJ2CON[0] [3:0] 0011 = Reserved, 0100 = CF_D[0] 0000 1111 = NWU_INT18[0]...
  • Page 93 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Field Description Reset Value 0000 = Input, 0001 = Output, 0010 = MSM_D[13] GPJ3CON[5] [23:20] 0011 = Reserved, 0100 = CF_D[13], 0000 1111 = NWU_INT19[5] 0000 = Input, 0001 = Output, 0010 = MSM_D[14]...
  • Page 94 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.1.27 Port Group GPK1 Configuration Register (GPK1CON, R/W, Address = 0xE030_02C0) Field Description Reset Value GPK1CON[0] [3:0] 0000 = Input, 0001 = Output, 0010 = EBI_Ben[0] 0010 GPK1CON[1] [7:4] 0000 = Input, 0001 = Output, 0010 = EBI_Ben[1]...
  • Page 95 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.1.30 Port Group GPL0 Configuration Register (GPL0CON, R/W, Address = 0xE030_0320) Field Description Reset Value GPL0CON[0] [3:0] 0000 = Input, 0001 = Output, 0010 = EBI_A[0] 0010 GPL0CON[1] [7:4] 0000 = Input, 0001 = Output, 0010 = EBI_A[1]...
  • Page 96 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) GPL3CON[1] [7:4] 0000 = Input, 0001 = Output, 0010 = EBI_D[4] 0010 GPL3CON[2] [11:8] 0000 = Input, 0001 = Output, 0010 = EBI_D[5] 0010 GPL3CON[3] [15:12] 0000 = Input, 0001 = Output, 0010 = EBI_D[6]...
  • Page 97 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL • GPH3DAT, R/W, Address = 0xE030_0C64. • GPIDAT, R/W, Address = 0xE030_01E4 • GPJ0DAT, R/W, Address = 0xE030_0204 • GPJ1DAT, R/W, Address = 0xE030_0224 • GPJ2DAT, R/W, Address = 0xE030_0244 • GPJ3DAT, R/W, Address = 0xE030_0264 •...
  • Page 98 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) • GPG3PUD, R/W, Address = 0xE030_01C8. • GPH0PULL, R/W, Address = 0xE030_0C08. • GPH1PULL, R/W, Address = 0xE030_0C28. • GPH2PULL, R/W, Address = 0xE030_0C48. • GPH3PULL, R/W, Address = 0xE030_0C68. • GPIPUD, R/W, Address = 0xE030_01E8.
  • Page 99 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL • GPF3DRV, R/W, Address = 0xE030_014C. • GPG0DRV, R/W, Address = 0xE030_016C. • GPG1DRV, R/W, Address = 0xE030_018C. • GPG2DRV, R/W, Address = 0xE030_01AC. • GPG3DRV, R/W, Address = 0xE030_01CC. • GPH0DRV, R/W, Address = 0xE030_0C0C.
  • Page 100 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) • GPF0PDNCON, R/W, Address = 0xE030_00F0. • GPF1PDNCON, R/W, Address = 0xE030_0110. • GPF2PDNCON, R/W, Address = 0xE030_0130. • GPF3PDNCON, R/W, Address = 0xE030_0150. • GPG0PDNCON, R/W, Address = 0xE030_0170. • GPG1PDNCON, R/W, Address = 0xE030_0190.
  • Page 101 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL • GPF0PDNPULL, R/W, Address = 0xE030_00F4. • GPF1PDNPULL, R/W, Address = 0xE030_0114. • GPF2PDNPULL, R/W, Address = 0xE030_0134. • GPF3PDNPULL, R/W, Address = 0xE030_0154. • GPG0PDNPULL, R/W, Address = 0xE030_0174. • GPG1PDNPULL, R/W, Address = 0xE030_0194.
  • Page 102 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.3 PORT GROUP MP REGISTERS Port Group Signal Port Group Signal DDR_CKE[0] DDR_D[9] MP1_0[0] MP1_4[2] DDR_CKE[1] DDR_D[10] MP1_0[1] MP1_4[3] DDR_SCLK DDR_D[11] MP1_0[2] MP1_4[4] DDR_nSCLK DDR_D[12] MP1_0[3] MP1_4[5] DDR_CSn[0] DDR_D[13] MP1_0[4] MP1_4[6] DDR_CSn[1] DDR_D[14] MP1_0[5]...
  • Page 103 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Port Group Signal Port Group Signal DDR_D[6] LD2_DQSn[0] MP1_3[7] MP1_8[1] DDR_D[7] LD2_DQSn[1] MP1_4[0] MP1_8[2] DDR_D[8] LD2_DQSn[2] MP1_4[1] MP1_8[3] LD2_DQSn[3] MP1_8[4] 5.3.1 Port Group MP1_X Drive Strength Control Register • MP1_0DRV, R/W, Address = 0xE030_03CC.
  • Page 104 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.4.2 Port Group ETC0 Drive strength control Register (ETC0DRV, R/W, Address = 0xE030_04EC) 00=1x, 01=2x, 10=3x, 11=4x. Field Description Reset Value ETC0DRV[0] [1:0] XjTRSTn Drive strength control register ETC0DRV[1] [3:2] XjTMS Drive strength control register...
  • Page 105 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL Reserved [7:6] Reserved 5.4.7 Port Group ETC3 Pull-up/down Register (ETC3PUD, R/W, Address = 0xE030_0548) 00 = Disables Pull-up/down, 01 = Enables Pull-down, 10 = Enables Pull-up Field Description Reset Value ETC3PUD[0] [1:0] XI2S0LRCK pin Pull-down control register...
  • Page 106 Interrupt is consists of 21 groups numbered from 0 to 20. Wake-up Interrupt consists of 32. In interrupt function, understanding the filter operation is essential. S5PC100 uses two types of filters to detect interrupt. They are delay filter and digital filter.
  • Page 107 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.5 Non wake-up Interrupt 4 Configuration Register (NWU_INT4_CON, R/W, Address = 0xE030_0710) Field Description Reset Value Sets the signaling method for NWU_INT4[n] (n=0,…,6) NWU_INT4_CON[6] [n*4+2:n*4] 000 = Low level, 001 = High level, 010 = Falling edge, 011 = Rising edge, 100 = Both edge 5.5.6 Non wake-up Interrupt 5 Configuration Register (NWU_INT5_CON, R/W, Address = 0xE030_0714)
  • Page 108 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.11 Non wake-up Interrupt 10 Configuration Register (NWU_INT10_CON, R/W, Address = 0xE030_0728) Field Description Reset Value Sets the signaling method for NWU_INT10[3] (n=0,…,3) NWU_INT10_CON[3] [n*4+2:n*4] 000 = Low level, 001 = High level, 010 = Falling edge, 011 = Rising edge, 100 = Both edge 5.5.12...
  • Page 109 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.17 Non wake-up Interrupt 16 Configuration Register (NWU_INT16_CON, R/W, Address = 0xE030_0740) Reset Field Description Value Sets the signaling method for NWU_INT16[n] (n=0,…,7) NWU_INT16_CON[7] [n*4+2:n*4] 000 = Low level, 001 = High level, 010 = Falling edge, 011 = Rising edge, 100 = Both edge 5.5.18...
  • Page 110 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.22 Non wake-up Interrupt 0 Filter Configuration Register 0 (NWU_INT0_FLTCON0, R/W, Address = 0xE030_0800) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN0[3] [31] Digital Filter Enable for NWU_INT0[3]...
  • Page 111 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL FLTEN1[0] Digital Filter Enable for NWU_INT1[0] NWU_INT1[0] [6:0] Filtering width for NWU_INT1[0] 5.5.25 Non wake-up Interrupt 1 Filter Configuration Register 1 (NWU_INT1_FLTCON1, R/W, Address = 0xE030_080C) The Digital Filter Enable field means that 0 = disables, 1 = enables.
  • Page 112 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.28 Non wake-up Interrupt 3 Filter Configuration Register 0 (NWU_INT3_FLTCON0, R/W, Address = 0xE030_0818) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN3[3] [31] Digital Filter Enable for NWU_INT3[3]...
  • Page 113 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.31 Non wake-up Interrupt 4 Filter Configuration Register 1 (NWU_INT4_FLTCON1, R/W, Address = 0xE030_0824) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value Reserved [31:24] Reserved...
  • Page 114 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.34 Non wake-up Interrupt 6 Filter Configuration Register 0 (NWU_INT6_FLTCON0, R/W, Address = 0xE030_0830) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN6[3] [31] Digital Filter Enable for NWU_INT6[3]...
  • Page 115 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.37 Non wake-up Interrupt 7 Filter Configuration Register 1 (NWU_INT7_FLTCON1, R/W, Address = 0xE030_083C) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN7[7] [31] Digital Filter Enable for NWU_INT7[7]...
  • Page 116 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) FLTEN8[4] Digital Filter Enable for NWU_INT8[4] NWU_INT8[4] [6:0] Filtering width for NWU_INT8[4] 5.5.40 Non wake-up Interrupt 9 Filter Configuration Register 0 (NWU_INT9_FLTCON0, R/W, Address = 0xE030_0848) The Digital Filter Enable field means that 0 = disables, 1 = enables.
  • Page 117 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL NWU_INT10[2] [22:16] Filtering width for NWU_INT10[2] FLTEN10[1] [15] Digital Filter Enable for NWU_INT10[1] NWU_INT10[1] [14:8] Filtering width for NWU_INT10[1] FLTEN10[0] Digital Filter Enable for NWU_INT10[0] NWU_INT10[0] [6:0] Filtering width for NWU_INT10[0] 5.5.43 Non wake-up Interrupt 11 Filter Configuration Register 0 (NWU_INT11_FLTCON0, R/W, Address = 0xE030_0858) The Digital Filter Enable field means that 0 = disables, 1 = enables.
  • Page 118 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.45 Non wake-up Interrupt 12 Filter Configuration Register 0 (NWU_INT12_FLTCON0, R/W, Address = 0xE030_0860) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value Reserved [31:24] Reserved...
  • Page 119 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.48 Non wake-up Interrupt 14 Filter Configuration Register 0 (NWU_INT14_FLTCON0, R/W, Address = 0xE030_0870) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN14[3] [31] Digital Filter Enable for NWU_INT14[3]...
  • Page 120 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.51 Non wake-up Interrupt 15 Filter Configuration Register 1 (NWU_INT15_FLTCON1, R/W, Address = 0xE030_087C) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN15[7] [31] Digital Filter Enable for NWU_INT15[7]...
  • Page 121 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL FLTEN16[4] Digital Filter Enable for NWU_INT16[4] NWU_INT16[4] [6:0] Filtering width for NWU_INT16[4] 5.5.54 Non wake-up Interrupt 17 Filter Configuration Register 0 (NWU_INT17_FLTCON0, R/W, Address = 0xE030_0888) The Digital Filter Enable field means that 0 = disables, 1 = enables.
  • Page 122 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.57 Non wake-up Interrupt 18 Filter Configuration Register 1 (NWU_INT18_FLTCON1, R/W, Address = 0xE030_0894) The Digital Filter Enable field means that 0 = disables, 1 = enables. Field Description Reset Value FLTEN18[7] [31] Digital Filter Enable for NWU_INT18[7]...
  • Page 123 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL NWU_INT19[5] [14:8] Filtering width for NWU_INT19[5] FLTEN19[4] Digital Filter Enable for NWU_INT19[4] NWU_INT19[4] [6:0] Filtering width for NWU_INT19[4] 5.5.60 Non wake-up Interrupt 20 Filter Configuration Register 0 (NWU_INT20_FLTCON0, R/W, Address = 0xE030_08A0) The Digital Filter Enable field means that 0 = disables, 1 = enables.
  • Page 124 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.65 Non wake-up Interrupt 4 Mask Register (NWU_INT4_MASK, R/W, Address = 0xE030_0910) Field Description Reset Value Reserved [31:7] Reserved NWU_INT4_MASK[n] 0 = Enabled, 1 = Masked (n=0,..,6) 5.5.66 Non wake-up Interrupt 5 Mask Register (NWU_INT5_MASK, R/W, Address = 0xE030_0914)
  • Page 125 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.72 Non wake-up Interrupt 11 Mask Register (NWU_INT11_MASK, R/W, Address = 0xE030_092C) Field Description Reset Value Reserved [31:8] Reserved NWU_INT11_MASK[n] 0 = Enabled, 1 = Masked (n=0,..,7) 5.5.73 Non wake-up Interrupt 12 Mask Register (NWU_INT12_MASK, R/W, Address = 0xE030_0930)
  • Page 126 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.79 Non wake-up Interrupt 18Mask Register (NWU_INT18_MASK, R/W, Address = 0xE030_0948) Field Description Reset Value Reserved [31:8] Reserved NWU_INT18_MASK[n] 0 = Enabled, 1 = Masked (n=0,..,7) 5.5.80 Non wake-up Interrupt 19 Mask Register (NWU_INT19_MASK, R/W, Address = 0xE030_094C)
  • Page 127 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.87 Non wake-up Interrupt 4 Pending Register (NWU_INT4_PEND, R/W, Address = 0xE030_0A10) Field Description Reset Value Reserved [31:7] Reserved NWU_INT4_PEND[n] 1 = Interrupt occurred (n=0,…,6) 5.5.88 Non wake-up Interrupt 5 Pending Register (NWU_INT5_PEND, R/W, Address = 0xE030_0A14)
  • Page 128 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.94 Non wake-up Interrupt 11 Pending Register (NWU_INT11_PEND, R/W, Address = 0xE030_0A2C) Field Description Reset Value Reserved [31:8] Reserved NWU_INT11_PEND[n] 1 = Interrupt occurred (n=0,…,7) 5.5.95 Non wake-up Interrupt 12 Pending Register (NWU_INT12_PEND, R/W, Address = 0xE030_0A30)
  • Page 129 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.101 Non wake-up Interrupt 18 Pending Register (NWU_INT18_PEND, R/W, Address = 0xE030_0A48) Field Description Reset Value Reserved [31:8] Reserved NWU_INT18_PEND[n] 1 = Interrupt occurred (n=0,…,7) 5.5.102 Non wake-up Interrupt 19 Pending Register (NWU_INT19_PEND, R/W, Address = 0xE030_0A4C)
  • Page 130 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.105 Non wake-up Interrupt Priority Control Register (NWU_INT_PRIORITY, R/W, Address = 0xE030_0B04) 0: Does not rotate(Fixed), 1: Enables rotate Field Description Reset Value Reserved [31:21] Reserved NWU_INT20_PRI [20] NWU_INT group 20 priority rotate enable...
  • Page 131 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL NWU_EINT12 NWU_EINT13 NWU_EINT14 NWU_EINT1 NWU_EINT15 NWU_EINT16 NWU_EINT17 NWU_EINT18 NWU_EINT19 NWU_EINT20 NWU_EINT2 NWU_EINT3 NWU_EINT4 NWU_EINT5 NWU_EINT6 NWU_EINT7 NWU_EINT8 SVC_Num [2:0] Interrupt number to be serviced 5.5.107 Non wake-up Interrupt Group Fixed Priority Control Register (NWU_INT_GRPFIXPRI, R/W,...
  • Page 132 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) Interrupt number of the highest priority in Non wake- Highest_EINT_NUM [2:0] up Interrupt Group 1 if fixed priority mode: 0~7 5.5.110 Non wake-up Interrupt 2 Fixed Priority Control Register (NWU_INT2_FIXPRI, R/W, Address = 0xE030_0B1C)
  • Page 133 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.115 Non wake-up Interrupt 7 Fixed Priority Control Register (NWU_INT7_FIXPRI, R/W, Address = 0xE030_0B30) Field Description Reset Value Reserved [31:3] Reserved Interrupt number of the highest priority in Non wake- Highest_EINT_NUM [2:0] up Interrupt Group 7 if fixed priority mode: 0~7 5.5.116 Non wake-up Interrupt 8 Fixed Priority Control Register (NWU_INT8_FIXPRI, R/W, Address =...
  • Page 134 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.5.120 Non wake-up Interrupt 12 Fixed Priority Control Register (NWU_INT12_FIXPRI, R/W, Address = 0xE030_0B44) Field Description Reset Value Reserved [31:3] Reserved Interrupt number of the highest priority in Non wake- Highest_EINT_NUM [2:0] up Interrupt Group 12 if fixed priority mode: 0~7 5.5.121 Non wake-up Interrupt 13 Fixed Priority Control Register (NWU_INT13_FIXPRI, R/W, Address =...
  • Page 135 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.5.125 Non wake-up Interrupt 17 Fixed Priority Control Register (NWU_INT17_FIXPRI, R/W, Address = 0xE030_0B58) Field Description Reset Value Reserved [31:3] Reserved Interrupt number of the highest priority in Non wake- Highest_EINT_NUM [2:0] up Interrupt Group 17 if fixed priority mode: 0~7 5.5.126 Non wake-up Interrupt 18 Fixed Priority Control Register (NWU_INT18_FIXPRI, R/W, Address =...
  • Page 136 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6 WAKE-UP INTERRUPT CONTROL REGISTERS Wake-up Interrupt consists of 32.(GPH0 ~ GPH3). These are used for wake-up source in Power down mode and, idle mode, all interrupts can be wake-up source, the other groups of Wake-up interrupts also can be the wake-up sources.
  • Page 137 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.2 Wake-up Interrupt Configuration Register8_15 (WKUP_INT_CON8_15, R/W, Address = 0xE030_0E04) 3 bits control 1 pin of Wake-up interrupt as follows, 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered...
  • Page 138 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6.3 Wake-up Interrupt Configuration Register16_23 (WKUP_INT_CON16_23, R/W, Address = 0xE030_0E08) 3 bits control 1 pin of Wake-up interrupt as follows, 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered...
  • Page 139 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.4 Wake-up Interrupt Configuration Register24_31 (WKUP_INT_CON24_31, R/W, Address = 0xE030_0E0C) 3 bits control 1 pin of Wake-up interrupt as follows, 000 = Low level 001 = High level 010 = Falling edge triggered 011 = Rising edge triggered...
  • Page 140 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6.5 Wake-up Interrupt Filter Configuration Register0_3 (WKUP_INT_FLTCON0_3, R/W, Address = 0xE030_0E80) Field Description Reset Value Filter Enable for WKUP_INT[3] FLTEN0_3[3] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[3] FLTSEL0_3[3] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 141 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.6 Wake-up Interrupt Filter Configuration Register4_7 (WKUP_INT_FLTCON4_7, R/W, Address = 0xE030_0E84) Field Description Reset Value Filter Enable for WKUP_INT[7] FLTEN4_7[7] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[7] FLTSEL4_7[7] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 142 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6.7 Wake-up Interrupt Filter Configuration Register8_11 (WKUP_INT_FLTCON8_11, R/W, Address = 0xE030_0E88) Field Description Reset Value Filter Enable for WKUP_INT[11] FLTEN8_11[3] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[11] FLTSEL8_11[3] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 143 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.8 Wake-up Interrupt Filter Configuration Register12_15 (WKUP_INT_FLTCON12_15, R/W, Address = 0xE030_0E8C) Reset Field Description Value Filter Enable for WKUP_INT[15] FLTEN12_15[7] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[15] FLTSEL12_15[7] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 144 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6.9 Wake-up Interrupt Filter Configuration Register16_19 (WKUP_INT_FLTCON16_19, R/W, Address = 0xE030_0E90) Field Description Reset Value Filter Enable for WKUP_INT[19] FLTEN16_19[3] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[19] FLTSEL16_19[3] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 145 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.10 Wake-up Interrupt Filter Configuration Register20_23 (WKUP_INT_FLTCON20_23, R/W, Address = 0xE030_0E94) Field Description Reset Value Filter Enable for WKUP_INT[23] FLTEN20_23[7] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[23] FLTSEL20_23[7] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 146 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6.11 Wake-up Interrupt Filter Configuration Register24_27 (WKUP_INT_FLTCON24_27, R/W, Address = 0xE030_0E98) Field Description Reset Value Filter Enable for WKUP_INT[27] FLTEN24_27[3] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[27] FLTSEL24_27[3] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 147 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.12 Wake-up Interrupt Filter Configuration Register28_31 (WKUP_INT_FLTCON28_31, R/W, Address = 0xE030_0E9C) Field Description Reset Value Filter Enable for WKUP_INT[31] FLTEN28_31[7] [31] 0 = disables 1 = enables Filter Selection for WKUP_INT[31] FLTSEL28_31[7] [30] 0 = delay filter 1 = digital filter(clock count)
  • Page 148 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.6.13 Wake-up Interrupt Mask Register0_7 (WKUP_INT_MASK0_7, R/W, Address = 0xE030_0F00) Field Description Reset Value Reserved [31:8] Reserved Mask register for WKUP_INT[n] WKUP_INT_MASK0_7[n] 0 = Enabled,1 = Masked (n=0~7) 5.6.14 Wake-up Interrupt Mask Register8_15 (WKUP_INT_MASK8_15, R/W, Address = 0xE030_0F04)
  • Page 149 S5PC100 USER’S MANUAL (REV1.0) PAD CONTRL 5.6.19 Wake-up Interrupt Pending Register16_23 (WKUP_INT_PEND16_23, R/W, Address = 0xE030_0F48) Field Description Reset Value Reserved [31:8] Reserved This bit is set if WKUP_INT [n+16] is pending. WKUP_INT_PEND16_23[n] Writing ‘1’ makes this bit clear. (n=0~7) Note.
  • Page 150 PAD CONTROL S5PC100 USER’S MANUAL (REV1.0) 5.8 USB HOST 1.1 PIN CONTROL REGISTER 5.8.1 USB Host 1.1 Pad Configure Register (UHOST, R/W, Address = 0xE030_B68) Field Description Reset Value Reserved [7:5] Reserved USB_DMPD USB DM Pull-down control 0 = disables...
  • Page 151: Clock Controller

    CLOCK CONTROLLER 1 CLOCK DOMAIN S5PC100 consists of three bus parts. First part consists of Cortex A8, D0_BUS and D0_BUS-attached modules. Cortex A8 supports only synchronous mode so that Cortex A8 and D0_BUS must operate synchronously. Second part consists of D1_BUS and D1_BUS-attached modules. Final part, D2 domain, is for low-power audio play.
  • Page 152 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2 CLOCK DECLARATION The clocks in S5C100 are classified into following: • Clocks from clock pads, i.e., XusbXTI, XXTI, XXTI27, and XrtcXTI • Clocks from a Clock Management Unit (CMU), e.g., HCLKD0, HCLKD1, and etc •...
  • Page 153 SCLK_27M EPLL_ CLK HCLK, ARMCLK , SCLK_ HDMI SCLK_54M PCLK HCLKD 0 . PCLKD 0 IISCDCLK (0,1,2) GPIO AC97 PCMCDCLK (0,1) GPIO PADS CAMCLK OUT ac_bit_clk pwm_eclk AC 97 clock PAD PWM clock PAD Figure 2.3-2 S5PC100 Top-Level Clocks 2.3-3...
  • Page 154 Some of them are selected, pre-scaled, and provided to the corresponding modules. Products of AP typically use 12MHz as an input clock source of APLL, MPLL and EPLL. Samsung recommend 27MHz for input clock of HPLL. The following components are used to generate internal clocks: •...
  • Page 155 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER In typical S5PC100 applications: • APLL is used for Cortex A8 and D0_BUS domain (i.e., ARMCLK, HCLKD0, PCLKD0, HCLKD0_SECSS, and SCLK_ONENAND). • MPLL is used for D1_BUS domain clock (HCLKD1 and PCLKD1) and other peripheral clocks (i.e., audio IPs, SPI, and etc.).
  • Page 156 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 PLL For PLL’s, the following three types are used: • pll6522x for APLL • pll6545a for MPLL • pll6545a for EPLL • pll6545a for HPLL Above listed PLL’s is integer PLLs. APLL is especially for D0 clock domain, which has ARM. It can make 50MHz ~ 2GHz, 45:55 duty frequency.
  • Page 157 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 4.2 EXAMPLE PLL PMS VALUE FOR PLL6545A (MPLL) Table 2.3-2. MPLL PMS Value FIN(MHz) Target FOUT(MHz) FOUT 133 MHz 166 MHz 4.3 EXAMPLE PLL PMS VALUE FOR PLL6545A (EPLL) Table 2.3-3. EPLL PMS Value...
  • Page 158 PLL converts the low input frequency into a high-frequency clock required by S5PC100. The clock generator block has a built-in logic to stabilize the clock frequency after each system reset since it takes time before stabilized.
  • Page 159 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER Figure 2.3-3 S5PC100 Clock Generation Circuit1 2.3-9...
  • Page 160 ARM_HPM, HPM) Related SFRs are CLKDIV_IEM_L1 ~ CLKDIV_IEM_L8. Audio_CMU is an additional clock generation circuit in S5PC100. This resides at D2 sub system for low-power MP3 play. For more information refer to “Section 7.2”. Figure 2.3-4 S5PC100 Clock Generation Circuit2 Table 2.3-5.
  • Page 161 CLK_DIV2 [31:0] = target value2; Can change PMS value (procedure 3), dividing value (procedure 4, 5) freely without stopping clock. 6.1 CLOCK GATING S5PC100 can disable the clock operation of each IP if it is not required. This reduces dynamic power. 2.3-11...
  • Page 162 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7 DETAILED CLOCK DESCRIPTION 7.1 CPU AND BUS CLOCK Cortex A8 supports only synchronous mode between CPU and bus (D0 Sync at Figure 2.3-5). D0 and D1 are asynchronous to each other. Figure 2.3-5 CPU and Bus Clock Some clocks can be gated by using SFR.
  • Page 163 Clock sources of Audio_CMU are EPLL output clock, clock from PAD, and SCLK_AUDIO0 (Refer to “Section 7.10”). Clock source of I2S is dependent to I2S mode. If S5PC100 is operated as I2S master mode, EPLL supplies I2S clock. If S5PC100 is operated as I2S slave mode, external I2S master supplies I2S clock. Bus clocks, HCLKD2 and PCLKD2, are asynchronous to I2S clock.
  • Page 164 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.3 SPECIAL CLOCK TABLE The Table 2.3-7 summarizes special clocks in S5PC100. Table 2.3-7 Special Clock in S5PC100 Name Description Input range Source SCLK_ONENAND, OneNAND controller ~88MHz (ONENAND_2) (A, M)PLL SCLK_ONENAND_2 operation clock ~166MHz (ONENAND)
  • Page 165 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER CPAD means external crystal or oscillator input for system PLLs or USB OTG PHY. PAD_27 means 27MHz crystal pad for TV-out. VCLK_54 is generated from clock-doubler. Audio pad means I2S and PCM codec clock.
  • Page 166 S5PC100 USER’S MANUAL (REV1.0) 7.5 TV CLOCK S5PC100 gets 27MHz-clock source to make 54MHz-clock for SDTV out. Internal clock-doubler doubles 27MHz- clock, and then passes 54MHz-clock to VDAC and TV out module. HDMI needs 27, 74.176, and 74.25 MHz clock. 74.176 and 74.25MHz are usually made by HPLL (HDMI PLL).
  • Page 167 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 7.6 FIMD AND FIMC CLK54M SCLK_LCD HPLLout MPLLout EPLLout CLK54M SCLK_FIMC0 HPLLout W0_LCLK MPLLout FIMC0 DCLK EPLLout HCLKD1 CLK54M SCLK_FIMC1 HPLLout FIMD W1_LCLK MPLLout FIMC1 DCLK EPLLout HCLKD1 CLK54M SCLK_FIMC2 HPLLout W2_LCLK MPLLout FIMC2...
  • Page 168 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Figure 2.3-10 LCD Subsystem Clock (for Setting) Use SFR to gate Special clocks. Table 2.3-8. LCD and FIMC Clock Gating SFR Clock Related SFR SCLK_FIMC0 CLK_GATE_SCLK_1[1] SCLK_FIMC1 CLK_GATE_SCLK_1[2] SCLK_FIMC2 CLK_GATE_SCLK_1[3] SCLK_LCD CLK_GATE_SCLK_1[0] 7.7 SECURE SUB-SYSTEM CLOCK Modules in Secure Sub-System Clock (SECSS) have long combinational paths because secure algorithm needs intensive computation.
  • Page 169 7.8 USB PHY AND 48MHZ CLOCK S5PC100 has an USB PHY for USB OTG. It has an internal PLL to generate clock for USB-OTG operation. Internal PLL must get definite clock-frequency (OSC 12, 24, and 48MHz / crystal 12MHz) through XusbXTI and XusbXTO.
  • Page 170 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.10 AUDIO CLOCK S5PC100 has three I2S (one for 5.1ch), two PCM, one AC97, and one SPDIF. Clock for those modules can be PLL output clock or input clock from PAD. CLK_SRC0[0] APLL APLL...
  • Page 171 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 7.11 MIPI CLOCK MIPI D-PHY has an internal PLL which generates MIPI clock for high-speed transmission with meeting tight jitter spec. Input clock for that PLL is TV reference clock (27MHz). 7.12 PERIPHERAL S5PC100x has many kinds of peripherals to communicate with external device, such as USB, MMC, UART, and etc.
  • Page 172 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Use SFR to gate Special clocks. Table 2.3-10. Peripheral Clock Gating SFR Clock Related SFR SCLK_CAM CLK_GATE_SCLK_0[12] SCLK_SPI0, SCLK_SPI1, SCLK_SPI2 CLK_GATE_SCLK_0[4], CLK_GATE_SCLK_0[5], CLK_GATE_SCLK_0[6] SCLK_UART CLK_GATE_SCLK_0[3] SCLK_MMC0, SCLK_MMC1, CLK_GATE_SCLK_0[12], CLK_GATE_SCLK_0[13], SCLK_MMC2 CLK_GATE_SCLK_0[14] SCLK_IRDA CLK_GATE_SCLK_0[10] SCLK_PWI...
  • Page 173 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 8 I/O DESCRIPTION Funtion Description Type Signal CLKOUT Clock monitoring pad XCLKOUT Dedicated XTI & XTO Input & XXTI & XXTO Dedicated Oscillator pads for system clock Output USB_XTI & Input & XusbXTI &...
  • Page 174 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Rs=0ohm, Rf=1Mohm, CL=10~35pF 2.3-24...
  • Page 175 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 9 REGISTER DESCRIPTION System controller controls PLL, clock generator, the power management part, and other system dependent part. This section describes how to control these parts using Special Functional Register (SFR) within the system controller.
  • Page 176 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value 0xE010_03FC 1.5 Clock output 0xE010_0400 CLK_OUT 0xE010_0400 Select clock output 0x0000_0000 0xE010_0404 Reserved Reserved 0x0000_0000 0xE010_04FC 1.6 Clock gating 0xE010_0500 Control HCLKD0 / PCLKD0 clock gating 0 CLK_GATE_D0_0 0xE010_0500...
  • Page 177 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 9.2 (OHTERS) REGISTER MAP – CLOCK CONTROLLER Register Address Description Reset Value 2.1 SW RESET registers 0xE020_0000 SWRESET 0xE020_0000 Generate software reset 0x0000_0000 Reserved 0xE020_0004 Reserved 0x0000_0000 ONENAND_SWRESET 0xE020_0008 OneNAND controller setting 0x0000_0000 0xE020_000C...
  • Page 178 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10 INDIVIDUAL REGISTER DESCRIPTIONS 10.1 PLL CONTROL REGISTERS S5PC100 has four internal PLLs, which are APLL, MPLL, EPLL, and HPLL. They are controlled by the following eight special registers. 10.1.1 PLL Lock • Control PLL locking period for APLL (APLL_LOCK, R/W, Address = 0xE010_0000) •...
  • Page 179 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.1.2 Control PLL Output Frequency for APLL (APLL_CON, R/W, Address = 0xE010_0100) PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates output after PLL locking period. The output frequency of PLL is controlled by the MDIV, PDIV, and SDIV values.
  • Page 180 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.1.3 Control PLL Output Frequency • Control PLL output frequency for MPLL (MPLL_CON, R/W, Address = 0xE010_0104) • Control PLL output frequency for EPLL (EPLL_CON, R/W, Address = 0xE010_0108) • Control PLL output frequency for HPLL (HPLL_CON, R/W, Address = 0xE010_010C) •...
  • Page 181 10.2 CLOCK SOURCE CONTROL REGISTER S5PC100 has many clock sources, which include four PLL outputs, the external oscillator, the external clock, and other clock sources from GPIO. CLK_SRC0, 1, 2, and 3 registers control the source clock of each clock divider.
  • Page 182 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.2.2 Select Clock Source 1 (Connectivity) (CLK_SRC1, R/W, Address = 0xE010_0204) Connectivity clock source register CLK_SRC1 Description Reset Value Reserved [31:25] Reserved Control MUX , which is the source clock of 48M CLK48M_SEL [24]...
  • Page 183 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.2.3 Select Clock Source 2 (Multimedia and Connectivity) (CLK_SRC2, R/W, Address = 0xE010_0208) Multimedia and Connectivity clock source register. CLK_SRC2 Description Reset Value Reserved [31:30] Reserved Control MUX , which is the source clock of MIXER...
  • Page 184 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.2.4 Select Clock Source 3 (Audio and Others) (CLK_SRC3, R/W, Address = 0xE010_020C) Audio and Others clock source register CLK_SRC3 Description Reset Value Reserved [31:26] Reserved Control MUX SPDIF SPDIF_SEL [25:24] (00:CLKAUDIO0, 01: CLKAUDIO1, 10:CLKAUDIO2)
  • Page 185 CLOCK CONTROLLER 10.3 CLOCK DIVIDER CONTROL REGISTER S5PC100 has several clock dividers to support various operating clock frequency. CLK_DIV0, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, and CLK_DIV_5 controls clock divider ratio. There are operating frequency limitations. The maximum operating frequency of DOUT...
  • Page 186 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.3.2 Set Clock Divider Ratio 1 (Main D1 domain) (CLK_DIV1, R/W, Address = 0xE010_0304) Main D1 domain divider CLK_DIV1 Description Reset Value Reserved [31:29] Reserved clock divider ratio, CAM_RATIO [28:24] CLKCAM = DOUT / RATIO (RATIO = CAM_RATIO + 1)
  • Page 187 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.3.3 Set Clock Divider Ratio 2 (Connectivity) (CLK_DIV2, R/W, Address = 0xE010_0308) Connectivity divider CLK_DIV2 Description Reset Value Reserved [31:24] Reserved UHOST1.1 clock divider ratio, UHOST [23:20] _RATIO CLKUHOST = UHOSTMUX/ RATIO (RATIO =UHOST_RATIO + 1)
  • Page 188 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.3.5 Set Clock Divider Ratio 4 (Audio and Others) (CLK_DIV4, R/W, Address = 0xE010_0310) Audio and Others divider CLK_DIV4 Description Reset Value Reserved [31:24] Reserved clock divider ratio, AUDIO2 AUDIO2_RATIO [23:20] CLKAUDIO2 = CLKAUDIO2...
  • Page 189 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.4 CLOCK OUTPUT CONFIGURATION REGISTER Internal clocks can be monitored through XCLKOUT PAD. CLK_OUT register selects an internal clock from PLL outputs, ARMCLK, HCLKD0, HCLKD1, PCLKD0, PCLKD1, 30MHz, 48MHz, 27MHz, 54MHz, RTC, and TICK. It also divides the selected clock.
  • Page 190 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) CLKOUT frequency = CLKIN (selected by CLKSEL) frequency / (DIVVAL+1) Figure 2.3-15 CLKOUT Waveform with DCLK Divider 10.5 CLOCK GATING CONTROL REGISTER The following three registers controls clock disable/ enable operation. 10.5.1 Control HCLKD0 / PCLKD0 Clock Gating 0 (System1) (CLK_GATE_D0_0, R/W, Address =...
  • Page 191 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.5.3 Control PCLKD0 Clock Gating 2 (System2) (CLK_GATE_D0_2, R/W, Address = 0xE010_0508) D0 domain System2 clock gating CLK_GATE_D0_2 Description Reset Value Reserved [31 : 3] Reserved CLK_SDM Gating HCLK & PCLKEN for SDM (0: Mask, 1: Pass)
  • Page 192 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.5.7 Control HCLKD1 / PCLKD1 Clock Gating 2 (Multimedia2) (CLK_GATE_D1_2, R/W, Address = 0xE010_0528) D1 domain Multimedia2 system clock gating CLK_GATE_D1_2 Description Reset Value Reserved [31 : 5] Reserved CLK_MFC Gating HCLK & PCLK for MFC (0: Mask, 1: Pass)
  • Page 193 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.5.9 Control HCLKD1 / PCLKD1 Clock Gating 2 (Connectivity) (CLK_GATE_D1_4, R/W, Address = 0xE010_0530) D1 domain connectivity system clock gating CLK_GATE_D1_4 Description Reset Value Reserved [31:14] Reserved CLK_HSIRX [13] Gating PCLK for MIPI_HSI receiver (0: mask, 1: pass)
  • Page 194 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.5.10 Control HCLKD1 / PCLKD1 Clock Gating 2 (Audio) (CLK_GATE_D1_5, R/W, Address = 0xE010_0534) D1 domain audio system clock gating CLK_GATE_D1_5 Description Reset Value Reserved [31:10] Reserved Reserved Reserved CLK_KEYIF Gating PCLK for Key IF (0: mask, 1: pass)
  • Page 195: Sclk_Uart

    S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.5.14 Control SCLK Clock Gating (System) (CLK_GATE_SCLK_0, R/W, Address = 0xE010_0560) System Special clock gating CLK_GATE_SCLK_0 Description Reset Value Reserved [31:18] Reserved Gating special clock 48MHz for MMC2 SCLK_MMC2_48 [17] (0: mask, 1: pass)
  • Page 196 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.5.15 Control SCLK Clock Gating (Multimedia) (CLK_GATE_SCLK_1, R/W, Address = 0xE010_0564) Multimedia Special clock gating CLK_GATE_SCLK_1 Description Reset Value Reserved [31:13] Reserved SCLK_CAM [12] Gating special clock for Camera (0: mask, 1: pass) SCLK_SPDIF...
  • Page 197 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.6.4 General Status Register (GENERAL_STATUS, R, Address = 0xE020_0104) GENERAL_STATUS Description Reset Value Reserved [31:14] Do not change this value 18’b0 TRIGGER [13] ETM trigger flag 1’b0 0 = Trigger does not occur 1 = Trigger occurs...
  • Page 198 CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 10.6.6 Camera Mapping to FIMC Selection (CAM_MUX_SEL, R/W, Address = 0xE020_0300) CAM_MUX_SEL Description Reset Value Reserved [31:2] Reserved Camera interface demuxing selection CAM_MUX_SEL [1:0] 0x00 (0 : FIMC0, 1 : FIMC1, 2 : FIMC2) 10.6.7 Video Mixer Output to TVENC / HDMI Selection (MIXER_OUT_SEL, R/W, Address = 0xE020_0304)
  • Page 199 S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER 10.6.10 MIPI D-PHY Control Register1 (MIPI_PHY_CON1, R/W, Address = 0xE020_0414) MIPI_PHY_CON1 Description Reset Value Master PPI I/F signal. If it is high, the clock signal from M_EXTSERCLK is selected for serial clock for the Master lane instead of...
  • Page 200: Power Management

    POWER MANAGEMENT 1 OVERVIEW The mobile application processor such as S5PC100 needs to consume low power since a mobile product has a small battery and limited power capacity. The purpose of power management is to provide various power saving methods to S5PC100 in consuming power as low as possible under specific application scenarios.
  • Page 201 Power Management S5PC100 USER’S MANUAL (REV1.0) A8, SRAM and other hard macros are controlled as explained in “Section 6 HARD MACRO POWER CONTROL”. Power Management controls the power mode of SRAM, ROM, PLL, TS ADC and I/O. The power mode of hard macros except SRAM, ROM, PLL, TS ADC and I/O should be controlled by corresponding control module.
  • Page 202 Therefore power to that domain is not supplied. The switch cells are controlled by setting registers (NORMAL_CFG, and STOP_CFG) in PMU. Note that external power to S5PC100 is not off. Therefore, there can be two power off techniques as listed below. • Power off without state retention ♦...
  • Page 203 External power off means that power to S5PC100 is externally off using regulator or PMIC (Power Management IC). PMU in S5PC100 generates power control signal to regulator or PMIC. If external power off is applied, the states of Normal F/F and Retention F/F are lost. Therefore, if you want to save some important data, you should move those data to external memory, and restore those data when wakeup event occurs.
  • Page 204 The power mode of hard macros except SRAM, ROM, PLL, TS ADC and I/O should be controlled by corresponding control module. Note that in addition to PMU, CLKCON also controls the PLL. Table 2.4-2 S5PC100 Power Domains Power Domain Included Modules...
  • Page 205 3.1 OVERVIEW According to the power saving schemes and features explained in the “Section 2 FUNCTION DESCRIPTION”, S5PC100 provides six power modes: NORMAL, IDLE, DEEP-IDLE, STOP, DEEP-STOP, and SLEEP. Power modes are summarized in Table 2.4-3. In NORMAL mode, use module-based clock off, block-based power off and frequency scaling to reduce power consumption.
  • Page 206 S5PC100 USER’S MANUAL (REV1.0) Power Management Table 2.4-3 Power Mode Summary Power Mode NORMAL IDLE DEEP-IDLE STOP DEEP-STOP SLEEP External Core Run with IEM Standby Power off Standby Power off power off Cortex- Retention / Retention / External Run with IEM...
  • Page 207 Frequency scaling is done in PLL-by-PLL basis. Lower the operating frequency of the modules by changing the PLL P/M/S values. Changing a P/M/S value causes PLL lock operation which takes time 300us. S5PC100 stops its operation during the PLL lock period since the PLL output clock is masked. Refer to Chapter 2.3 Clock Strategy to know how to change P/M/S value, and related clock divider value.
  • Page 208 S5PC100 USER’S MANUAL (REV1.0) Power Management Power off status of each power domain is found in the BLK_PWR_STAT register. BLK_PWR_STAT is not updated until the power-up or power-down process is completed. NORMAL_CFG and BLK_PWR_STAT have different values while the power-up or power-down procedure is going on, and has the same value after the power state change is completed.
  • Page 209 Power Management S5PC100 USER’S MANUAL (REV1.0) If TOP_LOGIC_ON_DIDLE = 1’b0, some IP modules in Top domain loses their states in F/F, and the other IP modules keep their states in F/F after wakeup. Table 2.4-4 shows IP modules in Top domain that have retention F/Fs, and those modules keep their states in F/F after wakeup.
  • Page 210 S5PC100 USER’S MANUAL (REV1.0) Power Management 8. S/W sets initialization configurations in LPCON (DRAM controller) to access to/from DRAM. Table 2.4-5 IP Modules in Top Domain Having Normal F/Fs Normal Module Base address Normal Module Base address Chip ID / OM...
  • Page 211 Power Management S5PC100 USER’S MANUAL (REV1.0) Figure 2.4-1 EPLL operation diagram). After wakeup from DEEP-IDLE / DEEP-STOP mode, P/M/S setting to EPLL_CON(@0xE010_0108) should be done, and EPLL_EN should be enabled by setting ENABLE[31] to 1’b1 in that register. After these setting is done, EPLL_RET should be released by setting EPLL_RET_RELEASE[30] to 1’b1 in OTHERS register.
  • Page 212 S5PC100 USER’S MANUAL (REV1.0) Power Management To exit STOP mode: • Various types of wakeup sources are used. Wakeup sources referred in Section 5 WAKEUP SOURCES. Then PMU performs the following sequence to exit STOP mode. 1. Enables the OSC pads if disabled and waits for the OSC stabilization (around 1ms).
  • Page 213 In SLEEP mode, all power domains are powered down except for ALIVE and RTC, all PLLs are disabled, and the oscillators (OSCs) except that for the RTC are selectively disabled. Since the external regulator becomes off using control signal from S5PC100, you should consider waiting time for the regulator stabilization in the SLEEP mode wake-up using PWR_STABLE register.
  • Page 214 S5PC100 USER’S MANUAL (REV1.0) Power Management 1. Asserts wake-up reset to low. 2. XPWRRGTON becomes high to power on external voltage regulator. 3. Waits for voltage regulator to be stable. 4. Enables the OSC pads if disabled and waits for the OSC stabilization (around 1ms.) 5.
  • Page 215 Power Management S5PC100 USER’S MANUAL (REV1.0) 4 SYSTEM POWER MODE TRANSITION Figure 2.4-2 shows the power mode transition diagram. Figure 2.4-2 Power Mode Transition Diagram The wakeup sources described in Figure 2.4-2 are summarized in Table 2.4-6. 2.4-16...
  • Page 216 S5PC100 USER’S MANUAL (REV1.0) Power Management 4.1 TRANSITION ENTERING / EXITING CONDITION Table 2.4-6 shows the Power Saving mode state and Entering or Exiting condition. As you can see, the entering conditions are set by the main ARM CPU. Table 2.4-6 Power Saving Mode Entering/Exiting Condition...
  • Page 217 Power Management S5PC100 USER’S MANUAL (REV1.0) Power Saving Enter Exit Mode 1. nBATF 2. External Interrupt 1. CFG_STANDBYWFI in PWR_CFG = 2'b11 SLEEP 3. RTC Alarm 2. PMU_INT_DISABLE in OTHERS = 1’b1 4. RTC TICK 3. ARM Command (WFI) 5. Key Pad Press event 1.
  • Page 218 Cortex-A8 to handle the external interrupt after wake up. 5.3 MODEM_IF The Base-band Modem Chip can wakeup Application Processor such as S5PC100 in power down mode as specified in Table 2.4-7. For more information of detailed wakeup sequence, refer to Chapter 8.11 MODEM INTERFACE manual.
  • Page 219 5.6 SYSTEM TIMER System Timer is newly introduced module in S5PC100 to supplement the disadvantage of the existing PWM timer. In IDLE mode, the existing PWM timer generates interrupts at fixed interval using auto-reload function, so it wakes up the chip too often.
  • Page 220 4. MIPI D-phy includes TX phy for DSI and RX phy for CSI. 5. For more information refer to “Section 6.9 Digital I/O”. Analog I/O is used to access to/from hard macros in S5PC100, and analog I/O power is supplied by separate analog I/O power pin.
  • Page 221 Power Management S5PC100 USER’S MANUAL (REV1.0) 6.1 SRAM SRAM in Top domain has four power modes: Run, Stand-by, Retention, and Power-down mode. • In Run mode, read and write access to SRAM are performed normally. • In Stand-by mode, SRAM chip select is deactivated, so that there is no read and write access.
  • Page 222 S5PC100 USER’S MANUAL (REV1.0) Power Management 6.3 USB OTG PHY Recommended power up sequence is shown in Figure 2.4-3. Figure 2.4-3 Power Up Sequence of USB OTG Phy USB OTG phy has three power modes: Run, IDLE, and Suspend mode.
  • Page 223 Power Management S5PC100 USER’S MANUAL (REV1.0) In NORMAL mode, all the three power modes can be used. If USB OTG phy is in use, then it is in Run mode if there is data transaction, and in IDLE mode if there is no data transaction.
  • Page 224 S5PC100 USER’S MANUAL (REV1.0) Power Management In IDLE mode and DEEP-IDLE mode (top domain on), MIPI D-phy keeps its operation or power state in NORMAL. Before entry to DEEP-IDLE mode (top domain off), STOP, and DEEP-STOP mode, it is recommended that MIPI D-phy enters into LP or ULPS mode.
  • Page 225 The behavior of EPLL in the other power down modes, is the same as the other PLLs (APLL, MPLL, HPLL). The initial-state of S5PC100 after wake-up from the SLEEP mode is almost the same as the Power-On-Reset state except for the contents of the external DRAM is preserved.
  • Page 226 In SLEEP mode, external power to TS ADC can be off. Power mode of TS ADC in SLEEP mode has no meaning. 6.9 DIGITAL I/O I/Os used in S5PC100 are divided into two groups, i.e., digital I/Os and analog I/Os, and digital I/Os are also divided into normal I/Os and alive I/Os.
  • Page 227 Power Management S5PC100 USER’S MANUAL (REV1.0) 6.9.2 Retention I/O, IO_RET_RELEASE, and SDMMC_IO_RET_RELEASE In DEEP-IDLE mode (top domain off), DEEP-STOP mode (top domain off) and SLEEP mode, GPIO setting to normal I/O is lost due to power off. (See Figure 2.4-4) Therefore, these setting should be saved before power to top domain is off (nSCALL_BLK_TOP = 1’b0), and restored after wakeup from power down mode if necessary.
  • Page 228 S5PC100 USER’S MANUAL (REV1.0) Power Management XusbXTI(XusbXTO) This I/O is dedicated pin, and therefore its value is kept during power down mode. 4) Analog I/O, dedicated : Xadc*, Xdac*, Xhdmi*, Xmipi*, Xusb*, Xuh*, Xef*, Xrtc*, Xcg* This I/O is dedicated pin, and therefore its value is kept during power down mode as long as analog power is supplied.
  • Page 229 • Hardware Reset – If XnRESET is driven to low it generates hardware reset. It is an uncompromised, ungated, total and complete reset that is used if you want to drive S5PC100 to a known initial state due to various reasons.
  • Page 230 NOTE : 1. The user should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during the power-on sequence. The S5PC100 assumes that the crystal oscillation is settled during the power-supply settle-down period. However, to ensure the proper operation during wake-up from the STOP...
  • Page 231 Power Management S5PC100 USER’S MANUAL (REV1.0) mode, the S5PC100 explicitly adds the crystal oscillator settle-down time (the wait-time is programmed using OSC_STABLE registers) after wake-up from the STOP mode. Table 2.4-13 Clock Timing Constants (VDD_INT= 1.2V± 0.05V, TA = -40 to 85°C, VDD_SYS0 = 3.3V ± 0.3V, 2.5V ± 0.2V, 1.8V ± 0.1V)
  • Page 232 Hardware reset is asserted when an external source drives the XnRESET input pin low. XnRESET is non- maskable, and therefore is always applicable. Upon assertion of XnRESET, S5PC100 enters into reset state regardless of the previous state. For hardware reset to be asserted actually, XnRESET must be held long enough to allow internal stabilization and propagation of the reset state.
  • Page 233 Power Management S5PC100 USER’S MANUAL (REV1.0) 7.3 SOFTWARE RESET Software reset is asserted when S/W writes "0xC100" to SWRESET register (@0xE020_0000) in NORMAL mode. During the software reset, the following actions occur: • All units (except some registers listed in Table 2.4-15) go into their pre-defined reset state.
  • Page 234 Watchdog reset is asserted if software fails to prevent the watchdog timer from timing out. In watchdog reset all units in S5PC100 (except some registers listed in Table 2.4-15) are reset to their predefined reset states. The behavior after Watchdog reset is asserted, is the same as Hardware reset case (Refer to “Section 7.1 HARDWARE RESET”).
  • Page 235 Power Management S5PC100 USER’S MANUAL (REV1.0) 7.5 WAKEUP RESET Wakeup reset is asserted when a module that has normal F/Fs is powered down, and the module is powered up again by wakeup events. Note that if the module has only retention F/Fs, wakeup reset is not asserted. But in sleep mode, wakeup reset is generated to all modules that were powered off regardless of normal F/F or retention F/F.
  • Page 236 S5PC100 USER’S MANUAL (REV1.0) Power Management GPH0_CON, GPH1_CON, GPH2_CON, GPH3_CON, GPH0_PAD_OUT, GPH1_PAD_OUT, GPH2_PAD_OUT, GPH3_PAD_OUT, GPH0_PAD_EN, GPH1_PAD_EN, GPH2_PAD_EN, GPH3_PAD_EN, GPH0_PAD_CPU, GPIO GPH1_PAD_CPU, GPH2_PAD_CPU, GPH3_PAD_CPU, GPH0_PAD_CPD, GPH1_PAD_CPD, GPH2_PAD_CPD, GPH3_PAD_CPD, GPH0_PAD_DRV, GPH1_PAD_DRV, GPH2_PAD_DRV, GPH3_PAD_DRV Others 1. Unlike INFORM0~3 registers, INFORM4-7 registers keep their values as long as alive power is supplied.
  • Page 237 Power Management S5PC100 USER’S MANUAL (REV1.0) 8 WAKEUP TIMING DIAGRAM In this section, wakeup timing diagrams from various power-down modes are described. 8.1 IDLE MODE WAKEUP Figure 2.4-9 shows wakeup timing from IDLE mode. In IDLE mode, ARMCLK is disabled for reducing dynamic power in ARM CPU. When wakeup event is asserted, ARMCLK_OFF signal is released and then ARMCLK is supplied for ARM CPU within XXTI 6 cycles.
  • Page 238 S5PC100 USER’S MANUAL (REV1.0) Power Management 8.2 DEEP-IDLE MODE WAKEUP Wakeup timing in DEEP-IDLE mode (Top domain on) is shown in Figure 2.4-10, and wakeup timing in DEEP- IDLE mode (Top domain off) is shown in Figure 2.4-11. Note that in Figure 2.4-10, ARMCLK is the same as those before DEEP-IDLE mode, but in Figure 2.4-11 ARMCLK is the same as XXTI after wakeup and APLL should be enabled to supply high-frequency for ARM CPU.
  • Page 239 Power Management S5PC100 USER’S MANUAL (REV1.0) . . . XXTI DEEP _IDLE _MODE ( internal ) XEINT [0] (wakup event) S / W sets P , M , S value and enable APLL ARMCLK _OFF ( internal ) . . .
  • Page 240 S5PC100 USER’S MANUAL (REV1.0) Power Management 8.3 STOP MODE WAKEUP Figure 2.4-12 shows wakeup timing from STOP mode. When wakeup source is asserted, ARMCLK is supplied for ARM CPU within some interval (refer to comment on Figure 2.4-12). ARMCLK is the same as those before STOP mode. After ARMCLK is supplied, CPU operation begins normally.
  • Page 241 Power Management S5PC100 USER’S MANUAL (REV1.0) 8.4 DEEP-STOP MODE WAKEUP Wakeup timing in DEEP-STOP mode (Top domain on) is shown in Figure 2.4-13..XXTI DEEP _ STOP _ MODE (internal ) XEINT [0 ] ( wakup event )
  • Page 242 In SLEEP mode, XPWRRGTON becomes low and then external power (VDDINT/ARM/PLL) is off to minimize leakage power of S5PC100. When SLEEP_WAKEUP is asserted, XPWRRGTON becomes high and then external power is on. ARMCLK is supplied for ARM and ARM_ARESETn is released within some interval (refer to...
  • Page 243 Power Management S5PC100 USER’S MANUAL (REV1.0) comment in Figure 2.4-5). After ARM_ARESETn is released, CPU operation begins normally. VDD_IO VDDALIVE XPWRRGTON VDDINT/ARM/PLL . . . XXTI SLEEP_MODE (internal) XEINT[0] S/W sets P,M,S value (wakup event) and enable APLL..
  • Page 244 S5PC100 USER’S MANUAL (REV1.0) Power Management Oscillation setting time from sleep mode return is shown in Figure 2.4-16. Main clock can be supplied by XXTI input (XOM[0]=0) or XusbXTI input (XOM[0]=1), and oscillator (EXTCLK) or crystal (OSC) can be used for main clock.
  • Page 245 Power Management S5PC100 USER’S MANUAL (REV1.0) 9 I/O DESCRIPTION Function Signal Description Type PWRRGTON Output External Power Regulator (or PMIC) On XPWRRGTON Dedicated nRSTOUT Output Internal Reset Out XnRSTOUT Dedicated nBATF Input Battery Fault XnBATF Dedicated nRESET Input External Hardware Reset...
  • Page 246 S5PC100 USER’S MANUAL (REV1.0) Power Management Register Address Description Reset Value 0xE010_811C- Reserved Reserved 0xE010_81FC OTHERS 0xE010_8200 Miscellaneous control register 0x0000_001E 0xE010_8204- Reserved Reserved 0xE010_82FC RST_STAT 0xE010_8300 Reset status register 0x0000_0001 WAKEUP_STAT 0xE010_8304 Wakeup status registers 0x0000_0000 BLK_PWR_STAT 0xE010_8308 Block power status register...
  • Page 247 Power Management S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value APLL_CON_L1 0xE010_861C ARM PLL Control (Performance Level : 1) 0x0190_0302 IEM_CONTROL 0xE010_8620 IEM Control Register 0x0000_0000 0xE010_8624- Reserved Reserved 0xE010_86FC CLKDIV_IEM_L8 0xE010_8700 Clock Divider for IEM(Performance Level : 8)
  • Page 248 S5PC100 USER’S MANUAL (REV1.0) Power Management 10.1 POWER MODE CONTROL REGISTER 10.1.1 Configure Power Manager (PWR_CFG, R/W, Address = 0xE010_8000) PWR_CFG Description Reset Value Configures DEEP setting for Cortex-A8 Core. (applied only to IDLE mode) CFG_DEEP_IDLE [31] 0 = No DEEP (Cortex-A8 core power on) 1= DEEP (Cortex-A8 core power off) Configures Top domain state in DEEP-IDLE mode.
  • Page 249 Power Management S5PC100 USER’S MANUAL (REV1.0) PWR_CFG Description Reset Value HSI_RX wake-up mask HSI_WAKEUP_MASK [13] 0 = HSI_RX is used as a wakeup source 1 = HSI_RX cannot be used as a wakeup source Touch screen Pen down (TS_PENDN) wake-up mask...
  • Page 250 S5PC100 USER’S MANUAL (REV1.0) Power Management PWR_CFG Description Reset Value If the configuration supports E-SLEEP, the system will entry E-SLEEP mode when nBATF is asserted (nBATF == 0). Configure wakeup source from E-SLEEP mode 0 = No wakeup source 1 = use all SLEEP wakeup sources except nBATF...
  • Page 251 Power Management S5PC100 USER’S MANUAL (REV1.0) 10.1.3 Configure Power Manager at Normal Mode (NORMAL_CFG, R/W, Address = 0xE010_8010) NORMAL_CFG Description Reset Value Reserved [31:24] Reserved 0x00 Reserved [23:8] DO NOT CHANGE 0xFFFF Reserved [7:6] DO NOT CHANGE Audio Sub-system : I2S0, SRAM (128 KB)
  • Page 252 S5PC100 USER’S MANUAL (REV1.0) Power Management 1. Top Memory On bit must be applied with Top domain On configuration. Top memory includes all SRAM inside IP module of Top domain. If TOP_MEMORY_ON = 0, then you should determine power mode (retention or off) of each TOP memory by setting STOP_MEM_CFG register before entering STOP/DEEP-STOP mode.)
  • Page 253 Power Management S5PC100 USER’S MANUAL (REV1.0) (2) DEEP-STOP_mode : ARM_LOGIC_ON[17] = 1’b0 TL[8] TM[31] AL[17] AM[29] Result X (AL=1, AL should be 0) X (AL=1, AL should be 0) X (TL=0 and TM=1) X (TL=0 and TM=1) X (AL=1, AL should be 0)
  • Page 254 S5PC100 USER’S MANUAL (REV1.0) Power Management (2) XXTI27: This pad is not affected by OSCUSB_EN(PWR_CFG[24]). OSC27_EN (PWR_CFG[0]) = 1'b0 OSC27_EN (PWR_CFG[0]) = 1'b1 OSC_EN_STOP = 1'b0 OSC_EN_STOP = 1'b1 OSC_EN_STOP = 1'b0 OSC_EN_STOP = 1'b1 OSC_EN OSC_EN OSC_EN OSC_EN OSC_EN...
  • Page 255 Power Management S5PC100 USER’S MANUAL (REV1.0) 10.1.6 Configure Memory Power at STOP mode (STOP_MEM_CFG, R/W, Address = 0xE010_801C) STOP_MEM_CFG Description Reset Value Reserved [31:11] Reserved CCAN [10] CCAN Block Memory control (0 = Off, 1 = Retention) IRDA IRDA Block Memory control (0 = Off, 1 = Retention)
  • Page 256 S5PC100 USER’S MANUAL (REV1.0) Power Management 10.2.2 Oscillation Pad Stable Counter (OSC_STABLE, R/W, Address = 0xE010_8104) OSC_STABLE Description Reset Value Reserved [31:20] Reserved Mapping to counter value 19 to 4 when STABLE COUNTER [19:4] Type is 1 (OSC_CNT_VALUE[3:0] should stay at reset...
  • Page 257 If external power is supplied from off state, it takes some amount of time for the external regulator or PMIC to supply stable power. PWR_STABLE register is applied to wait for this power stabilization time when S5PC100 is exit from SLEEP mode.
  • Page 258 S5PC100 USER’S MANUAL (REV1.0) Power Management 10.2.5 CorTex-A8 CLAMP Stable Counter (CLAMP_STABLE, R/W, Address = 0xE010_8114) CLAMP_STABLE Description Reset Value Reserved [31:28] Reserved Reserved [27:26] Reserved Clamp off counter value. This value is used in power-up sequence. This field is set to as follows:...
  • Page 259 Power Management S5PC100 USER’S MANUAL (REV1.0) OTHERS Description Reset Value kept in those power down mode. Then, you should set this bit to 1 so that EPLL can be used normally. 0 = auto clear by h/w, 1 = de-assert EPLL_RET...
  • Page 260 S5PC100 USER’S MANUAL (REV1.0) Power Management OTHERS Description Reset Value to 1 so that SDMMC I/O pads can be used normally. 0 = auto clear by h/w, 1 = de-assert SDMMC_IO_RET Reserved [21:17] DO NOT CHANGE 0x0000 The role of this bit is to bypass or block the signals transferred from USB OTG PHY to internal logic.
  • Page 261 Power Management S5PC100 USER’S MANUAL (REV1.0) 10.4 STATUS REGISTER 10.4.1 Reset Status Register (RST_STAT, R, Address = 0xE010_8300) RST_STAT Description Reset Value Reserved [31:8] Reserved DIDLE_WAKEUP ARM Reset from Deep IDLE DSTOP_WAKEUP ARM Reset from Deep STOP SWRESET Software reset by SWRESET...
  • Page 262 S5PC100 USER’S MANUAL (REV1.0) Power Management BLK_PWR_STAT Description Reset Value Block LCD power ready Block G3D power ready Block MFC power ready Reserved Reserved 10.5 INFORMATION REGISTER • Information Register 0 (INFORM0, R/W, Address = 0xE010_8400) • Information Register 1 (INFORM1, R/W, Address = 0xE010_8404) •...
  • Page 263 Power Management S5PC100 USER’S MANUAL (REV1.0) 10.5.3 DCGIDX_MAP2 Register (DCGIDX_MAP2, R/W, Address = 0xE010_8508) This register is related to IECCFGDCGIDXMAP[95:64] of IEM_IEC input port. DCGIDX_MAP2 Description Reset Value dcgidx_map2 [31:0] IEC configuration for DCG index map [95:64] 0xFFFF_FFFF dcgidx_map2[31:0] is mapped to IECCFGDCGIDXMAP[95:64] of IEM_IEC input port.
  • Page 264 S5PC100 USER’S MANUAL (REV1.0) Power Management Table 2.4-16 IECCFGFREQCPU Examples IECCFGFREQCPU[23:0] Verilog expression Processor frequency 0x004E20 24'd020_000 20000kHz = 20MHz 0x03A980 24'd240_000 240000kHz = 240MHz 0x0003E8 24'd001_000 1000kHz = 1MHz 10.5.8 FREQ_DPM Register (FREQ_DPM, R/W, Address = 0xE010_851C) The register related to IECCFGFREQDPM[23:0] of IEM_IEC input port.
  • Page 265 Power Management S5PC100 USER’S MANUAL (REV1.0) 10.5.10 APLL_CON_L8 Register (APLL_CON_L8, R/W, Address = 0xE010_8600) The register configures P/M/S values for ARM PLL at IEM performance level of 8. APLL_CON_L8 Description Reset Value Reserved [31:28] Reserved Reserved [27:26] Reserved apll_mval_l8 [25:16]...
  • Page 266 S5PC100 USER’S MANUAL (REV1.0) Power Management 10.5.12 IEM_CONTROL Registerbn (IEM_CONTROL, R/W, Address = 0xE010_8620) The register controls IEM global function. IEM_CONTROL Description Reset Value Reserved [31:28] Reserved Reserved [27:26] Reserved Reserved [25:24] DO NOT CHANGE IEM previous target performance level setting. You can set...
  • Page 267 Power Management S5PC100 USER’S MANUAL (REV1.0) CLKDIV_IEM_L8 Description Reset Value Reserved DO NOT CHANGE This field is used to set dividing value in both DIV ARM_HPM. clock divider ratio, DOUT = DOUT / RATIO APLL arm_div_val_l8 [6:4] (RATIO = arm_div_val_l8 + 1), and...
  • Page 268 S5PC100 USER’S MANUAL (REV1.0) Power Management 10.5.14 CLKDIV_IEM_L1-7 Register • Clock Divider for IEM (Performance Level -7) (CLKDIV_IEM_L7, R/W, Address = 0xE010_8704) • Clock Divider for IEM (Performance Level -6) (CLKDIV_IEM_L6, R/W, Address = 0xE010_8708) • Clock Divider for IEM (Performance Level -5) (CLKDIV_IEM_L5, R/W, Address = 0xE010_870C) •...
  • Page 269 Power Management S5PC100 USER’S MANUAL (REV1.0) 10.5.15 IEM_HPMCLK_DIV Register (IEM_HPMCLK_DIV, R, Address = 0xE010_8724) The register reads the current IEM HPMCLK divider value. IEM_HPMCLK_DIV Description Reset Value Reserved [31:4] Reserved 0x0000_000 Reserved Reserved iem_hpmclk_div [2:0] IEM HPMCLK Divider Value 2.4-70...
  • Page 270 S5PC100 USER’S MANUAL (REV1.0) Power Management 11 POWER MODE APPLICATION FOR SCENARIO In this section, we describe how to apply system power mode for a specific operation scenario to consume as the minimum power as possible, for easy understanding. We consider a several operation scenario: Audio playback, Video playback, and Camcorder Recording.
  • Page 271 Power Management S5PC100 USER’S MANUAL (REV1.0) 11.2 VIDEO PLAYBACK Power Mode NORMAL IDLE DEEP-IDLE L2RETENTION / STANDBY POWER-OFF ← ← Power on ← ← Power on / Power-gating ← ← Audio Sub-system Power on ← ← LCD Sub-system Power on ←...
  • Page 272 IEM supports eight performance levels. It depends on system and application how many performance levels you use. To implement clock change scheme, PMU in S5PC100 has 22 registers (6 registers for IEM configurations, 8 registers for PLL P/M/S value, and 8 register for clock dividers). Among 22 registers, 9 registers for IEM configurations are common to all performance levels, and two registers (one for PLL P/M/S value, the other for clock divider) are assigned to each performance level.
  • Page 273 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT INTELLIGENT ENERGY MANAGEMENT 1 OVERVIEW The IEM solution is designed primarily for battery powered equipment, where the requirement to have as long a battery life as possible is paramount. The IEM solution is ideal for portable applications, for example smartphones, feature phones, Personal Digital Assistants (PDA), hand held games consoles and portable media players.
  • Page 274 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) These parts of the system cooperate with each other to optimize power consumption, without compromising on performance or responsiveness. Simply, an IEM system works as follows: • When the IEM software starts, it registers some kernel hooks with the OS.
  • Page 275 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 1.2 BLOCK DIAGRAM AMBA APB Bus Maximum performance request Target Frequency Acknowledge Index ARM Core clock Clock Current Configuration Information HPM clock Management Frequency Index Unit Target Frequency Index Intelligent Power Current Frequency Index...
  • Page 276 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) FUNCTIONAL DESCRIPTIONS To support IEM, S5PC100 includes special IPs as below: • Power Management Unit supporting IEM • Intelligent Energy Controller • Clock Management Unit supporting Dynamic Clock Generation ♦ Clock Management Unit in System Controller acts as Dynamic Clock Generator •...
  • Page 277 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT hardware. The IEC provides an encoded performance index to SoC specific CMU and APC1 blocks. The IEC also includes a Design for Test (DFT) interface. This enables easier control over the scaling hardware during production testing of the SoC device.
  • Page 278 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 2.1.2 Advanced Power Controller In S5PC100X, Advanced Power Controller (APC1) from National Semiconductor is used for Dynamic Voltage Control. The APC1 is an advanced power controller designed for reuse in the AMBA-based designs with a standard APB slave interface for programming registers.
  • Page 279 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT • supports the closed-loop AVS voltage control in conjunction with the HPM • voltage table to support the open-loop DVS • supports thermometer-encoded interface for a target performance level request and a current performance level update •...
  • Page 280 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 2.1.4 Power Management Unit In S5PC100X, the Power Management Unit (PMU) supports IEM features. The PMU provides the IEC with configuration information, for example: • fractional index map, indicating the fractional levels supported •...
  • Page 281 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 2.2 IEM SYSTEM OPERATION Loading and starting the software At an appropriate stage of system boot-up, the OS loads and initializes the modules that contain the IEM software: • on most platforms, the module loader automatically runs the initialization code for a module (if any) •...
  • Page 282 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) • creates a structure describing the system event • ensures that there is an IEM block describing the corresponding task • runs the fast event handlers to process the system event. The kernel hook then determines whether any standard event handlers recognize the system event. If so, the kernel hook adds the event to the event queue, for subsequent processing by the standard event handlers.
  • Page 283 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT The standard event handler then processes the event, analyzing the data in the IEM kernel data structures and any data that was stored by the fast event handler to determine the optimum performance level. The analysis that the standard event handler performs is usually very different to that performed by the fast event handler of the same policy.
  • Page 284 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 3 IEM IMPLEMENTATION AND DRIVER SETTING 3.1 DEFINITION OF PERFORMANCE The maximum frequency of APLL is 1.6GHz. The expected frequency range of ARM Core is from 166MHz to 800MHz. AXI_D0 bus, which is connected to ARM Core, works at 166MHz.
  • Page 285 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 3.2 HPM STRUCTURE AND CLOSED-LOOP BEHAVIOR When IEM works with closed-loop, HPM and APC1 work like as Figure 2.5-4 and Figure 2.5-5. integral_reg[20:0] ([20:14]=closedloop_vdd) rst_filterq | integral = hpm_targetclk_c ((integral > 22’h1F_C000) integral_reg + 21’h1F_C000...
  • Page 286 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) clkdivcnt[5:0] apc_target_index[7:0] clkdivcnt == clock_div || 6’h00 APC_SLK_SMP (apc_target_index != apc_target_index_prv) apc_target_index_prv clkdivcnt APC_UNSHT_NOISE[5:4] noise_limit_int clock_div default 5’h00 5’h04 step_dir_int = 0 precnt = < cnt = Integral = 0 5’h10 step_upward = 0...
  • Page 287 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 3.2.1 HPM Delay Critical path delay of ARM Core in S5PC100X is about 1.70ns in the worst condition. Delay of NOR2X1 cell is about 0.04609ns. One delay tap has four NOR2X1 cells and each delay tap gives 0.184ns delay. Delay tap structure is as shown in Figure 2.5-6.
  • Page 288 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 3.4 PWI (POWER WISE INTERFACE) The PWI master drives the PWI clock line. Although a pull-down resistor is connected between the SCLK and GND-voltage on the slave, the PWI master drives the clock signal actively high and low.
  • Page 289: X8000

    S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5 REGISTER DESCRIPTION 5.1 REGISTER SUMMARY Table 2.5-3 Register Summary of IEC Register Address Description Reset value IECDPCCR 0xE110_0000 DPC Control Register 0x000000E0 IECDVSEMSTR 0xE110_0004 DVS Emulation Slot Time Register 0x63 IECDPCTGTPERF 0xE110_0008...
  • Page 290 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset value IECPeriphID7 0xE110_0FDC Peripheral Identification Register 7 Reserved IECPeriphID0 0xE110_0FE0 Peripheral Identification Register 0 0x50 IECPeriphID1 0xE110_0FE4 Peripheral Identification Register 1 0x17 IECPeriphID2 0xE110_0FE8 Peripheral Identification Register 2 0x04...
  • Page 291 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT Table 2.5-4 Register Summary of APC Register Address Description Reset value APC_PWICMD 0xE100_0000 PWI Command Register 0x00 APC_PWIDATAWR 0xE100_0004 PWI Write Data Register 0x00 APC_PWIDATARD 0xE100_0008 PWI Read Data Register 0x00 APC_CONTROL 0xE100_0010...
  • Page 292 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset value APC_PL4_COREVDD 0xE100_00AC Open-loop VDD Core Register 4 0x7F APC_PL5_COREVDD 0xE100_00B0 Open-loop VDD Core Register 5 0x7F APC_PL6_COREVDD 0xE100_00B4 Open-loop VDD Core Register 6 0x7F APC_PL7_COREVDD 0xE100_00B8 Open-loop VDD Core Register 7...
  • Page 293 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.2 IEC RELATED REGISTERS 5.2.1 DPC Control Register (IECDPCCR, R/W, Address = 0xE110_0000) IECDPCCR Bits Description Reset Value Reserved [31:8] Reserved, read undefined, do not modify. Max Performance [7:5] When IECMAXPERF goes high, the IEC requests maximum mapping index performance level which is decided by this register value.
  • Page 294 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) maximum performance. 5.2.2 DVS Emulation Slot Time Register (IECDVSEMSTR, R/W, Address = 0xE110_0004) IECDVSEMSTR Bits Description Reset Value Reserved [31:10] Reserved, read undefined, do not modify. The time in μs for each slot of a PWM frame. This is reset...
  • Page 295 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.2.6 Raw Interrupt Status Register (IECRIS, R, Address = 0xE110_0014) IECRIS Bits Description Reset Value Reserved [31:2] Reserved, read undefined, do not modify. CPU Sleep Interrupt Returns the raw interrupt state prior to masking of Status (CSRIS) IECCPUSLPINT interrupt.
  • Page 296 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.2.10 DPM Frequency Register (IECDPMFREQ, R, Address = 0xE110_0024) IECDPMFREQ Bits Description Reset Value Reserved [31:24] Reserved, read undefined, do not modify. DPM Frequency (DPMF) [23:0] The DPM frequency in kHz. From PMU 5.2.11 Configuration Fractional Index Map00 Register (IECCFGDCGIDXMAP00, R, Address =...
  • Page 297 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.2.17 DPM Command Register (IECDPMCR, R/W, Address = 0xE110_0100) IECDPMCR Bits Description Reset Value Reserved [31:12] Reserved, read undefined, do not modify. DPMCH3CMD [11:8] DPM Channel 3 command. DPMCH2CMD [7:4] DPM Channel 2 command.
  • Page 298 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.2.22 DPM Channel Registers (IECDPM2LO, R, Address = 0xE1100_0188) IECDPM2LO Bits Description Reset Value IECDPM2LO [31:0] Low 32-bit of DPM channel 2. 0x00000000 The reset value is 0x00000000. 5.2.23 DPM Channel Registers (IECDPM2HI, R, Address = 0xE1100_018C)
  • Page 299 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.2.26 Peripheral Identification Register 0 (IECPeriphID0, R, Address = 0xE110_0FE0) IECPeriphID0 Bits Description Reset Value Reserved [31:8] Reserved, read undefined, do not modify. Partnumber0 [7:0] These bits read back as 0x50 0x50 5.2.27 Peripheral Identification Register 1 (IECPeriphID1, R, Address = 0xE110_0FE4)
  • Page 300 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.2.32 Peripheral Identification Register 6 (IECPeriphID6, R, Address = 0xE110_0FD8) IECPeriphID6 Bits Description Reset Value Reserved [31:8] Reserved, read undefined, do not modify. Configuration 4 [7:0] These bits are all reserved Reserved 5.2.33 Peripheral Identification Register 7 (IECPeriphID7, R, Address = 0xE110_0FDC)
  • Page 301 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.3 APC1 RELATED REGISTERS 5.3.1 PWI Command Register (APC_PWICMD, R/W, Address = 0xE100_0000) APC_PWICMD Bits Description Reset Value PWI Slave Register Address [7:4] PWI slave Register address of the read and write register.
  • Page 302 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.3.4 APC Control Register (APC_CONTROL, R/W, Address = 0xE100_0010) APC_CONTROL Bits Description Reset Value APC_HPM_AUTH_SE HPM is set to the ring oscillator mode for a random PC used in the authentication sequence. APC_PWRSV_EN Enables the power save mode.
  • Page 303 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.3.6 Minimum Limit Register (APC_MINVDD_LIMIT, R/W, Address = 0xE100_0018) APC_MINVDD_LIMIT Bits Description Reset Value Reserved Read undefined. Write as zero. Minimum core voltage [6:0] Minimum SoC operating core voltage. 0x00 5.3.7 VDD Check Register (APC_VDDCHK, R/W, Address = 0xE100_001C)
  • Page 304 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.3.11 APC Interrupt Status Register (APC_ISTATUS, R, Address = 0xE100_002C) APC_ISTATUS Bits Description Reset Value Reserved Read undefined. APB Write Discard When the PWI command is active in the APC1, the new PWI commands issued by the host are discarded. This discarded status is reflected in this bit.
  • Page 305 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.3.13 APC Undershoot Threshold and Noise Limit Register (APC_UNSHT_NOISE, R/W, Address = 0xE100_0034) APC_UNSHT_NOISE Bits Description Reset Value Reserved [7:6] Read undefined. Write as zero. Noise Limit for [5:4] Noise limit for the VDDOK generation due to the power VDDOK supply regulation errors.
  • Page 306 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.3.17 APC Overshoot Limit Register (APC_OVSHT_LMT, R/W, Address = 0xE100_0050) APC_OVSHT_LMT Bits Description Reset Value overshoot limit [7:0] Overshoot limit during the voltage slew in the closed-loop 0x00 mode. 5.3.18 APC Closed-loop Control Register (APC_CLP_CTRL, R/W, Address = 0xE100_0054)
  • Page 307 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.3.20 Integrator’s Gain Registers (APC_IGAIN1, R/W, Address = 0xE100_0060) APC_IGAIN1 Bits Description Reset Value Reserved [7:4] Read undefined. Write as zero. Gain 1 [3:0] Default gain term for the dynamic compensator. The programmable values for this gain term are one to ten. Rest of the values are treated as zero in the closed-loop AVS operations.
  • Page 308 INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0) 5.3.24 Voltage Information Registers APC1 has two types of voltage information registers. Ones are for closed-loop control, and the others are for open-loop control. Registers for closed-loop control give delay information, while registers for open-loop control give direct voltage information.
  • Page 309 S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT 5.3.25 Retention VDD Registers (APC_RET_VDD, R/W, Address = 0xE100_00C0) APC_RET_VDD Bits Description Reset Value Reserved Read undefined. Write as zero. Retention VDD [6:0] The retention voltage level for performance level zero. 0x00 5.3.26 Debug Performance Registers (APC_DBG_DLYCODE, R, Address = 0xE100_00E0)
  • Page 310 S5PC100 USER’S MANUAL (REV1.0) BUS CONFIGURATION BUS CONFIGURATION 1 BUS CONFIGURATION OVERVIEW Figure 3.1-1 shows the bus architecture of S5PC100. This chapter describes the feature & programmer’s model of AXI interconnects used in this product. D2 clock domain Perspective Descriptions on Bus Architecture:...
  • Page 311 BUS CONFIGURATION S5PC100 USER’S MANUAL (REV1.0) In S5PC100, the QoS scheme will be used for restricting the transactions of the background operation when there is heavy real time traffic. The masters attached to AXI_B0 are classified as background operation which requires a high bandwidth but does not require to be real time traffic.
  • Page 312 S5PC100 USER’S MANUAL (REV1.0) BUS CONFIGURATION 2 PROGRAMMABLE FEATURES OF AXI INTERCONNECT 2.1 PROGRAMMABLE QUALITY OF SERVICE The QoS scheme works by tracking the number of outstanding transactions, and when a specified number is reached, it only permits transactions from particular, specified masters.
  • Page 313 BUS CONFIGURATION S5PC100 USER’S MANUAL (REV1.0) 2.2 ARBITRATION SCHEME In the AXI interconnect, you can configure each MI separately to have an arbitration scheme that is either: • a non-programmable RR scheme • a programmable LRG scheme. The AW and AR channels have separate arbiters and can be programmed, if applicable, and interrogated separately through the APB programming interface, but both AW and AR channels are configured identically.
  • Page 314 S5PC100 USER’S MANUAL (REV1.0) BUS CONFIGURATION 2.3 ROUND-ROBIN (RR) SCHEME In the RR scheme, you can select the following design time: • The number of slots that are used • The SI to which they are allocated • The order of slots.
  • Page 315 BUS CONFIGURATION S5PC100 USER’S MANUAL (REV1.0) 2.3.1 Least Recently Granted (LRG) Scheme In the LRG scheme, each connected SI has a single slot associated with it, but each interface also has a priority value. This priority value, whose post-reset value can be configured at design time and programmed or interrogated through the APB programming interface, can make the arbiter behave as: •...
  • Page 316 S5PC100 USER’S MANUAL (REV1.0) BUS CONFIGURATION 3 REGISTER DESCRIPTION 3.1 AXI_D0 REGISTER MAPS Register Address Description Reset Value QOSTM_M0 0xE300_0400 QoS Tidemark for MI 0 0x00000000 QOSAC_M0 0xE300_0404 Qos Access control for MI 0 0x00000000 R_AR_M0 0xE300_0408 AR Channel Arbitration value for MI 0...
  • Page 317 BUS CONFIGURATION S5PC100 USER’S MANUAL (REV1.0) 3.2 AXI_D0 REGISTER DESCRIPTION 3.2.1 QoS Tidemark Registers for M0 (QOSTM_M0, R/W, Address = 0xE300_0400) QOSTM_M0 Description Reset Value Reserved - [31:6] Reserved QoS Tidemark [5:0] The number of outstanding transactions that are permitted before the QoS scheme becomes active.
  • Page 318 S5PC100 USER’S MANUAL (REV1.0) BUS CONFIGURATION 3.2.3 Channel Arbitration Registers (M0/M1/M2, W, Address = 0xE300_0408, 0xE300_040C, 0xE300_0428, 0xE300_042C, 0xE300_0448, 0xE300_044C) • Writes data case M0 / M1 / M2 Description Reset Value Slot [31:24] The slot for which the data is to be written...
  • Page 319 S5PC100 USER’S MANUAL (REV1.0) CORESIGHT CORESIGHT 1 CORESIGHT SYSTEM OVERVIEW 1.1 ABOUT CORESIGHT SYSTEMS GENERALS CoreSight systems provide all the infrastructure you require to debug, monitor, and optimize the performance of a complete System on Chip (SoC) design. There are historically three main ways of debugging an ARM processor based SoC: •...
  • Page 320 CORESIGHT S5PC100 USER’S MANUAL (REV1.0) 1.2 FEATURES 1.2.1 Debug Access You gain debug access in CoreSight systems through the Debug Access Port (DAP) that provides: • real-time access to physical memory without halting the core and without any target resident code •...
  • Page 321 1.3 CORESIGHT SYSTEM IN S5PC100 S5PC100 is single processor system with CortexA8 core. And it’s main bus system is based on AMBA3 AXI interconnects. And it does not support Serial Wire debug port protocol.
  • Page 322 CORESIGHT S5PC100 USER’S MANUAL (REV1.0) Figure 3.2-2 S5PC100 Coresight Structure 3.2-4...
  • Page 323 Figure 3.2-2, the memory map for system view is same as the memory map for JTAG port + system register offset. The debugger register map of S5PC100 is summarized in Figure 3.2-3. Figure 3.2-3 Debugger Register Map of S5PC100 The more detail information of debugger register will be handled in programmers model part.
  • Page 324 Before authentication, the debugger should access to internal authentication module in security sub system. In S5PC100, the AHB AP of coresight provides path for internal module to debugger as depicted in Figure 3.2-4. If Secure JTAG lock on bit is programmed as “1”, the authentication signals such as DBGEN, NIDEN, SPIDEN, SPNIDEN are all “0”...
  • Page 325 S5PC100 USER’S MANUAL (REV1.0) CORESIGHT Table 3.2-1 Authentication Signal Rule Secure Secure Mode JTAG lock Access DBGEN NIDEN SPIDEN SPNIDEN type JTAG & non-authenticated dont care 1'b0 1'b0 1'b0 1'b0 JTAG & authenticated as non-secure 1'b0 1'b1 1'b0 1'b0 non-invasive JTAG &...
  • Page 326 CORESIGHT S5PC100 USER’S MANUAL (REV1.0) * AHB AP is allowed to access only to Secure JTAG SFR region to avoid security hole before authentication. * The blue line access is available, while the red line accesses are not available AHB_RX...
  • Page 327 S5PC100 USER’S MANUAL (REV1.0) CORESIGHT 2 DEBUG ACCESS PORT 2.1 ABOUT DEBUG ACCESS PORT The Debug Access Port (DAP) is a implementation of an ARM Debug Interface version 5 (ADIv5) comprising a number of components supplied in a single configuration. All the supplied components fit into the various architectural components for Debug Ports (DPs), which are used to access the DAP from an external debugger and Access Ports (APs), to access on-chip system resources.
  • Page 328 CORESIGHT S5PC100 USER’S MANUAL (REV1.0) Figure 3.2-6 Structure of the Coresight DAP Components 3.2-10...
  • Page 329 S5PC100 USER’S MANUAL (REV1.0) CORESIGHT 3 ETB 3.1 ABOUT THE ETB The ETB provides on-chip storage of trace data using 32-bit RAM. Figure 3.2-7 shows the main ETB blocks. The ETB accepts trace data from CoreSight trace source components through an AMBA Trace Bus (ATB).
  • Page 330 CORESIGHT S5PC100 USER’S MANUAL (REV1.0) Figure 3.2-7 ETB Block Diagram 3.2-12...
  • Page 331 S5PC100 USER’S MANUAL (REV1.0) CORESIGHT 4 ECT (CTI + CTM) 4.1 ABOUT THE ECT The ECT provides an interface to the debug system as shown in Figure 3.2-8. This enables ARM subsystems to interact, that is cross trigger, with each other. The debug system enables debug support for multiple cores, together with cross triggering between the cores and their respective internal embedded trace macrocells.
  • Page 332 CORESIGHT S5PC100 USER’S MANUAL (REV1.0) 5 I/O DESCRIPTION Signal Description Type XjTRSTn Dedicated nTRST Input TAP reset XjTCK Dedicated Input TAP clock XjTMS Dedicated Input TAP test mode selection XjTDI Dedicated Input TAP data in XjTDO Dedicated Output TAP data out NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals.
  • Page 333 Limited. The TZPC provides a software interface to the protection bits in a secure system in a TrustZone design. It provides system flexibility that enables to configure different areas of memory as secure or non-secure. The S5PC100 comprises of three TZPC. 1.1 FEATURES 1.
  • Page 334 ACCESS CONTROLLER (TZPC) S5PC100 USER’S MANUAL (REV1.0) 2 FUNCTIONAL DESCRIPTION The TZPC provides a software interface to set up memory areas as secure or non-secure. The two ways to set up memory area as secure or non-secure is as follows: •...
  • Page 335 S5PC100 USER’S MANUAL (REV1.0) ACCESS CONTROLLER (TZPC) 3 TZPC CONFIGURATION The following table(Table 3.3-1) shows the configurable region. TZPC0 is configurable of TZPCDECPROT and TZPCR0SIZE. TZPC1 and TZPC2 are configurable of TPCDECPROT. Table 3.3-1 TZPC Table TZPC0 TZPC1 TZPC2 Register...
  • Page 336 ACCESS CONTROLLER (TZPC) S5PC100 USER’S MANUAL (REV1.0) The following table(Table 3.3-2) shows the fixed region with secure. Table 3.3-2 Secure Region Module Name Secure TZPC0 Secure TZPC1 Secure TZPC2 Secure CHIPID Secure SECKEY Secure MEM_SDMA Secure TZIC Secure SECSS Secure If non-secure master accesses to secure slave area, DECERR occurs.
  • Page 337 S5PC100 USER’S MANUAL (REV1.0) ACCESS CONTROLLER (TZPC) 4 REGISTER DISCRIPTION 4.1 SUMMARY OF REGISTERS Register Address Description Reset Value TZPC0 TZPCR0SIZE 0xE380_0000 Secure RAM Region Size Register 0x000003FF TZPCDECPROT0Stat 0xE380_0800 Decode Protection 0 Status Register 0x00000000 − TZPCDECPROT0Set 0xE380_0804 Decode Protection 0 Set Register −...
  • Page 338 ACCESS CONTROLLER (TZPC) S5PC100 USER’S MANUAL (REV1.0) TZPC2 TZPCR0SIZE 0xE290_0000 Not used 0x00000200 TZPCDECPROT0Stat 0xE290_0800 Decode Protection 0 Status Register 0x00000000 − TZPCDECPROT0Set 0xE290_0804 Decode Protection 0 Set Register − TZPCDECPROT0Clr 0xE290_0808 Decode Protection 0 Clear Register TZPCDECPROT1Stat 0xE290_080C Decode Protection 1 Status Register 0x00000000 −...
  • Page 339 S5PC100 USER’S MANUAL (REV1.0) ACCESS CONTROLLER (TZPC) 4.2 SECURE RAM REGION SIZE REGISTER • TZPCR0SIZE(TZPC0), RW, Address = 0xE380_0000 TZPCR0SIZE Description Reset Value Reserved [31:10] Read undefined. Write as zero. Secure RAM region size in 4KB steps. 0x00000000 = no secure region...
  • Page 340 ACCESS CONTROLLER (TZPC) S5PC100 USER’S MANUAL (REV1.0) 4.4 DECODE PROTECTION 0-2 SET REGISTERS • TZPCDECPROTxSet(TZPC0), W, Address = 0xE380_0804, 0xE380_0810 • TZPCDECPROTxSet(TZPC1), W, Address = 0xE280_0804, 0xE280_0810, 0xE280_081C • TZPCDECPROTxSet(TZPC2), W, Address = 0xE290_0804, 0xE290_0810 TXPCDECPROTxSet Description Reset Value −...
  • Page 341 S5PC100 USER’S MANUAL (REV1.0) ACCESS CONTROLLER (TZPC) TZPC PERIPHERAL IDENTIFICATION REGISTER 0 (TZPCPERIPHID0, R, ADDRESS = 0XE380_0FE0, 0XE280_0FE0, 0XE290_0FE0) TZPCPERIPHID0 Description Reset Value Reserved [31:8] Read undefined Partnumber0 [7:0] These bits read back as 0x70 0x70 4.7 TZPC PERIPHERAL IDENTIFICATION REGISTER 1...
  • Page 342 ACCESS CONTROLLER (TZPC) S5PC100 USER’S MANUAL (REV1.0) IDENTIFICATION REGISTER 0 (TZPCPCELLID0, R, ADDRESS = 0XE380_0FF0, 0XE280_0FF0, 0XE290_0FF0) TZPCPCELLID0 Description Reset Value Reserved [31:8] Read undefined TZPCPCELLID0 [7:0] These bits read back as 0x0D 0x0D 4.10 IDENTIFICATION REGISTER 1 (TZPCPCELLID1, R, ADDRESS = 0XE380_0FF4, 0XE280_0FF4, 0XE290_0FF4)
  • Page 343 The major features of the bridge include: • Single independent AXI master and AXI slave interfaces • All AXI channels are buffered independently • Configurable FIFO buffer depth for each AXI channel • Dynamic Synchronous Bypass mode. (S5PC100 does not use Bypass mode) 3.4-1...
  • Page 344 ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0) 1.2 BRIEF DESCRIPTION OF FUNCTION At the top level, the bridge comprises: • Five FIFOs, one for each AXI channel • Logic to manage transition (to and from Synchronous Bypass mode). There is no requirement for the bridge to examine any part of the data in an AXI channel. Therefore it can be treated as unstructured and consider each channel as valid, ready, and payload data.
  • Page 345 S5PC100 USER’S MANUAL (REV1.0) ASYNC BRIDGE Figure 3.4-2 Asynchronous Bridge Components 3.4-3...
  • Page 346 ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0) 1.3 OPERATION OF ASYNCHRONOUS BRIDGE 1.3.1 Normal Operation Almost all functionality is provided by the five logically identical FIFOs and this section describes their operation. Figure 3.4-3 shows the internal structure of a FIFO.
  • Page 347 S5PC100 USER’S MANUAL (REV1.0) ASYNC BRIDGE Each counter must be synchronized to the other clock domain because the counters are updated in different timing domains. The counters use a Gray code to ensure the safety of operation of the FIFOs, therefore the synchronization always captures either: •...
  • Page 348 ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0) Data is written into the FIFO. The write pointer update occurs. The first synchronization stage of this value to the read side occurs because enough time has elapsed since the write pointer updated. The second synchronization stage occurs and enables synchronized pointer visible to the read side.
  • Page 349 S5PC100 USER’S MANUAL (REV1.0) ASYNC BRIDGE • The second half of the sequence, positions N to 2N-1, is found by taking the value at position N-1, inverting its most significant bit and then XORing that with each value in the first half of the sequence. The first value in the second half of the sequence is the fullness value for the sequence.
  • Page 350 2 THE PERFORMANCE IMPROVEMENT OF ASYNC BRIDGE IN S5PC100 2.1 LATENCY REDUCTION The most outstanding architecture of S5PC100 is asynchronous clock scheme between D0 domain and D1 domain as shown in Figure 3.4-6. D0 domain is composed of high-speed memory system and the CPU system, while D1 domain is composed of multimedia systems including MFC, LCD, Camera interface and TV system whose performance largely depends on memory bandwidth.
  • Page 351 14.22 cycle by adopting 1/2 cycle synchronizer. In S5PC100 system, the 7~8% degradation of 3D engine is observed in the experiment which inserts the register slice between 3D engine and the DRAM (The full register slice increases total 2 cycles latency).
  • Page 352 Fortunately, these read data bubbles can be reduced by increasing read data FIFO size of Async Bridge. In S5PC100, the read data FIFO size is increased to 32. We assumed the worst case is the 4 successive 16burst is one bunch of transaction. And the 4 bunch of transaction are serviced with the 10 cycle interval between the bunch of transactions.
  • Page 353 It causes the bubbles in the write data channel. In S5PC100, in order to avoid the bubble condition, WREADY of Async Bridge’s slave part is delayed for proper cycles according to the clock speed rate of master and slave as shown in Figure 3.4-9.
  • Page 354 ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0) Second, the big bubble between the write address channel and the write data channel should be investigated. According to the AXI bus specification, the master issues the data of write transactions in the same order in which it issues the transaction addresses.
  • Page 355 S5PC100 USER’S MANUAL (REV1.0) ASYNC BRIDGE If the AXI interconnect’s arbitration scheme is priority base and Async Bridge has highest priority, Async Bridge is handled as a default master. In that case, the AXI interconnect can give WREADY signal to default master 1 cycle earlier than to other masters.
  • Page 356 ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0) 3 REGISTER DESCRIPTION Register Address Description Reset Value HALFSYNC 0xE340_0000 1/2 cycle synchronizer selection 0x00 ASYNC_INDEX 0xE340_0004 Async index register for write enhancing 0x00 DMASTER 0xE340_0008 Optimizing delay for default master 0x00 NOTE: If async bridge has highest priority in AXI interconnect, then async bridge is handled as a default master.
  • Page 357 VECTORED INTERRUPT CONTROLLER 1 OVERVIEW The interrupt controller in S5PC100 is composed of 3 VIC’s (Vectored Interrupt Controller, ARM PrimeCell PL192) and 3 TZIC’s (TrustZone Interrupt Controller, SP890). Three TZIC’s and three VIC’s are daisy-chained to support up to 94 interrupt sources. The TZIC provides a software interface to the secure interrupt system in a TrustZone design.
  • Page 358 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.2 BLOCK DIAGRAM Nonvectored FIQ FIQStatus[31:0] nVICFIQ interrupt logic IRQStatus[31:0] Interrupt Vectored interrupt 0 VICINTSOURCE[31:0] request Vectored interrupt 1 logic Vectored interrupt 31 IRQ vector IRQ & nVICIRQ address and VectAddr priority logic...
  • Page 359 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Figure 4.1-2 VIC Daisy Chain 4.1-3...
  • Page 360 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2 INTERRUPT SOURCE The S5PC100 supports interrupt sources as shown in the Table below. Module INT Request Description SDM_FIQ (security) SDM Security Violation Detect FIQ Interrupt SDM_IRQ (security) SDM Security Violation Detect IRQ Interrupt SEC_TX (security) Crypto Engine’s TX FIFO Interrupt...
  • Page 361 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Module INT Request Description Reserved MIPI_DSI MIPI DSI Interrupt MIPI_CSI MIPI CSI Interrupt HSMMC2 HSMMC2 Interrupt HSMMC1 HSMMC1 Interrupt HSMMC0 HSMMC0 Interrupt MODEM Modem I/F Interrupt OTG (usb) USB OTG Interrupt UHOST (usb)
  • Page 362 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Module INT Request Description Reserved GPIOINT All other GPIO Interrupt (ORed) RTC_TIC RTC TIC Interrupt RTC_ALARM RTC Alarm Interrupt Watchdog Timer Interrupt System Timer System Timer Interrupt Timer 4 Interrupt TIMER4 Timer 3 Interrupt...
  • Page 363 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER 3 FUNCTIONAL DESCRIPTION When user clears interrupt pending, user must write 0 to all the VICADDRESS registers (VIC0ADDRESS, VIC1ADDRESS, and VIC2ADDRESS). 4.1-7...
  • Page 364 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 REGISTER DESCRIPTION Register Address Description Reset Value VIC0IRQSTATUS 0xE400_0000 IRQ Status Register 0x00000000 VIC0FIQSTATUS 0xE400_0004 FIQ Status Register 0x00000000 VIC0RAWINTR 0xE400_0008 Raw Interrupt Status Register VIC0INTSELECT 0xE400_000C Interrupt Select Register 0x00000000 VIC0INTENABLE...
  • Page 365 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC0VECTADDR23 0xE400_015C Vector Address 23 Register 0x00000000 VIC0VECTADDR24 0xE400_0160 Vector Address 24 Register 0x00000000 VIC0VECTADDR25 0xE400_0164 Vector Address 25 Register 0x00000000 VIC0VECTADDR26 0xE400_0168 Vector Address 26 Register 0x00000000...
  • Page 366 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value VIC0VECTPRIORITY26 0xE400_0268 Vector Priority 26 Register VIC0VECTPRIORITY27 0xE400_026C Vector Priority 27 Register VIC0VECTPRIORITY28 0xE400_0270 Vector Priority 28 Register VIC0VECTPRIORITY29 0xE400_0274 Vector Priority 29 Register VIC0VECTPRIORITY30 0xE400_0278 Vector Priority 30 Register...
  • Page 367 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC1VECTADDR8 0xE410_0120 Vector Address 8 Register 0x00000000 VIC1VECTADDR9 0xE410_0124 Vector Address 9 Register 0x00000000 VIC1VECTADDR10 0xE410_0128 Vector Address 10 Register 0x00000000 VIC1VECTADDR11 0xE410_012C Vector Address 11 Register 0x00000000...
  • Page 368 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value VIC1VECTPRIORITY11 0xE410_022C Vector Priority 11 Register VIC1VECTPRIORITY12 0xE410_0230 Vector Priority 12 Register VIC1VECTPRIORITY13 0xE410_0234 Vector Priority 13 Register VIC1VECTPRIORITY14 0xE410_0238 Vector Priority 14 Register VIC1VECTPRIORITY15 0xE410_023C Vector Priority 15 Register...
  • Page 369 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC2INTSELECT 0xE420_000C Interrupt Select Register 0x00000000 VIC2INTENABLE 0xE420_0010 Interrupt Enable Register 0x00000000 VIC2INTENCLEAR 0xE420_0014 Interrupt Enable Clear Register VIC2SOFTINT 0xE420_0018 Software Interrupt Register 0x00000000 VIC2SOFTINTCLEAR 0xE420_001C Software Interrupt Clear Register...
  • Page 370 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value VIC2VECTADDR27 0xE420_016C Vector Address 27 Register 0x00000000 VIC2VECTADDR28 0xE420_0170 Vector Address 28 Register 0x00000000 VIC2VECTADDR29 0xE420_0174 Vector Address 29 Register 0x00000000 VIC2VECTADDR30 0xE420_0178 Vector Address 30 Register 0x00000000...
  • Page 371 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value VIC2VECTPRIORITY30 0xE420_0278 Vector Priority 30 Register VIC2VECTPRIORITY31 0xE420_027C Vector Priority 31 Register VIC2ADDRESS 0xE420_0F00 Vector Address Register 0x00000000 VIC2PERIPHID0 0xE420_0FE0 Peripheral Identification Register bit 7:0 0x92 VIC2PERIPHID1 0xE420_0FE4...
  • Page 372 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value TZIC0FIQStatus 0xE500_0000 FIQ Status Register 0x00000000 TZIC0RawIntr 0xE500_0004 Raw Interrupt Status Register TZIC0IntSelect 0xE500_0008 Interrupt Select Register 0x00000000 TZIC0FIQEnable 0xE500_000C FIQ Enable Register 0x00000000 TZIC0FIQENClear 0xE500_0010 FIQ Enable Clear Register...
  • Page 373 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER Register Address Description Reset Value TZIC2RawIntr 0xE520_0004 Raw Interrupt Status Register TZIC2IntSelect 0xE520_0008 Interrupt Select Register 0x00000000 TZIC2FIQEnable 0xE520_000C FIQ Enable Register 0x00000000 TZIC2FIQENClear 0xE520_0010 FIQ Enable Clear Register TZIC2FIQBypass 0xE520_0014 FIQ Bypass Register...
  • Page 374 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.1 IRQ STATUS REGISTER (VICIRQSTATUS, R, ADDRESS=0XE400_0000, 0XE410_0000, 0XE420_0000) VICIRQSTATUS Description Reset Value Shows the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: IRQStatus [31:0] 0 = Interrupt is inactive 0x00000000 1 = Interrupt is active.
  • Page 375 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER 4.4 INTERRUPT SELECT REGISTER (VICINTSELECT, R/W, ADDRESS=0XE400_000C, 0XE410_000C, 0XE420_000C) VICINTSELECT Description Reset Value Selects interrupt type for interrupt request: 0 = IRQ interrupt IntSelect [31:0] 0x00000000 1 = FIQ interrupt There is one bit of the register for each interrupt source.
  • Page 376 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.7 SOFTWARE INTERRUPT REGISTER (VICSOFTINT, R/W, ADDRESS=0XE400_0018, 0XE410_0018, 0XE420_0018) VICSOFTINT Description Reset Value Setting a bit HIGH generates a software interrupt for the selected source before interrupt masking. Read: 0 = Software interrupt inactive...
  • Page 377 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER 4.10 VECTOR ADDRESS REGISTER (VICADDRESS, R/W, ADDRESS=0XE400_0F00, 0XE410_0F00, 0XE420_0F00) VICADDRESS Description Reset Value Contains the address of the currently active ISR, with reset value 0x00000000. A read of this register returns the address of the ISR and sets the current interrupt as being serviced.
  • Page 378 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.14 VICPERIPHID0 REGISTER (VICPERIPHID0, R, ADDRESS=0XE400_0FE0, 0XE410_0FE0, 0XE420_0FE0) VICPERIPHID0 Description Reset Value [31:8] Reserved, read as 0, do not modify. Partnumber0 [7:0] These bits read back as 0x92 0x92 4.15 VICPERIPHID1 REGISTER (VICPERIPHID1, R, ADDRESS=0XE400_0FE4, 0XE410_0FE4, 0XE420_0FE4)
  • Page 379 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER 4.18 VICPCELLID0 REGISTER (VICPCELLID0, R, ADDRESS=0XE400_0FF0, 0XE410_0FF0, 0XE420_0FF0) VICPCELLID0 Description Reset Value [31:8] Reserved, read as 0, do not modify. VICPCellID0 [7:0] These bits read back as 0x0D. 0x0D 4.19 VICPCELLID1 REGISTER (VICPCELLID1, R, ADDRESS=0XE400_0FF4, 0XE410_0FF4, 0XE420_0FF4)
  • Page 380 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.23 RAW INTERRUPT STATUS REGISTER (TZICRAWINTR, R, ADDRESS=0XE500_0004, 0XE510_0004, 0XE520_0004) TZICRawIntr Description Reset Value Shows the status of the interrupts before masking by the TZICFIQIntEnable and TZICFIQIntEnClear Registers. RawIntr [31:0] A HIGH bit indicates that the interrupt is active before masking.
  • Page 381 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER 4.26 FIQ ENABLE CLEAR REGISTER (TZICFIQENCLEAR, W, ADDRESS=0XE500_0010, 0XE510_0010, 0XE520_0010) TZICFIQENClear Description Reset Value Clears bits in the TZICFIQEnable Register. Writing a HIGH clears the corresponding bit in the FIQEnClear [31:0] TZICFIQEnable Register.
  • Page 382 VECTORED INTERRUPT CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.30 LOCK STATUS REGISTER (TZICLOCKSTATUS, R, ADDRESS=0XE500_0020, 0XE510_0020, 0XE520_0020) TZICLockStatus Description Reset Value [31:1] Read undefined. Shows the locked status of the TZIC: 0 = Access to the TZIC is not locked Locked...
  • Page 383 S5PC100 USER’S MANUAL (REV1.0) VECTORED INTERRUPT CONTROLLER 4.34 PERIPHERAL IDENTIFICATION REGISTER (TZICPERIPHID3, R, ADDRESS=0XE500_0FEC, 0XE510_0FEC, 0XE520_0FEC) TZICPeriphID3 Description Reset Value [31:8] Read undefined Configuration [7:0] These bits read back as 0x00 4.35 IDENTIFICATION REGISTER (TZICPCELLID0, R, ADDRESS=0XE500_0FF0, 0XE510_0FF0, 0XE520_0FF0) TZICPCellID0...
  • Page 384 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER DRAM CONTROLLER 1 OVERVIEW 1.1 FEATURES • Compatible with JEDEC specification of DDR2, mDDR and LPDDR2 SDRAM • 32bit data width only • mDDR: up to 256Mbyte per 1 nCS (up to 2 nCS’s) •...
  • Page 385 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.2 BLOCK DIAGRAM Low Power AXI Low Power Channel Manager Bank FSM information Bank0 Control Queue Queue Arbiter (8/16 Final entries ) Arbiter AREF Bus Interface Block 32 bit DDR / DDR 2 /...
  • Page 386 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 2 FUNCTIONAL DESCRIPTION 2.1 INITIALIZATION An Initialization procedure consists of PHY DLL initialization, setting controller register and memory initialization. For memory initialization, please refer to JEDEC specifications and data sheets of memory devices. According to the memory types, initialization sequences are as follows.
  • Page 387 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.1.2 mDDR2 1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
  • Page 388 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 2.1.3 DDR2 1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
  • Page 389 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.2 ADDRESS MAPPING The controller modifies the address of the bus transaction coming from the AXI slave port into a memory address - chip select, bank address, row address, column address and memory data width.
  • Page 390 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 2.2.2 Interleaved Mapping AXI base address bank0.row0 row density bank1.row0 bank2.row0 bank3.row0 bank0.row1 AXI offset address bank1.row1 bank2.row1 bank3.row1 bank column width bank0.rown bank1.rown bank2.rown Interleaved mapping : AXI offset address = {row, bank, column , width} bank3.rown...
  • Page 391 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.3 LOW POWER OPERATION The controller executes a low power memory operation in five ways as described below. Each feature is independent of each other and executed at the same time. 2.3.1 AXI low Power Channel The controller has an AXI low power channel interface to communicate with low power management units such as the system controller, which makes the memory device go into self-refresh mode.
  • Page 392 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 2.4 PRECHARGE POLICY There are two ways for the controller to decide precharge policy. 2.4.1 Bank Selective Precharge Policy Since applications have different page policy preferences, it is hard for the engineer to decide whether to use open page policy, or close page (auto precharge) policy.
  • Page 393 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.5 QUALITY OF SERVICE QoS is defined for the CONTROLLER as a method to increase the arbitration priority of a master that requires low latency read data. The QoS is determined if the control queue (Refer to Figure 5.1-1) receives the command through the AXI bus and the QoS count starts depreciating at this moment.
  • Page 394 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 2.6 READ DATA CAPTURE A memory device that receives a read command sends the data to the controller after a read latency (i.e. CAS latency). After clearing the DQS, the PHY uses the PHY DLL to phase shift the DQS 90 degrees. Using the shifted DQS, the PHY samples the read data and saves the data into the read data input FIFO, which is located inside the PHY.
  • Page 395 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) To calculate the DDR2 rd_fetch value: rd_fetch DDR2) = INT((Delay + 0.5T + 0.25T)/T) = INT(Delay/T + 0.75), Delay: board delay + PHY input/output delay, T: clock period, INT(x): the rounded-up integer value of x Therefore, rd_fetch must have minimum one value.
  • Page 396 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER SDRAM command READ RL = 3 tDQSCK negedge negedge + Delay sampling sampling 90' phase shifted DQS RL + rd_fetch = 3 PHY read input FIFO {Q1, Q0} {Q3, Q2} AXI read channel {Q1, Q0} {Q3, Q2} Figure 5.1-9 Timing Diagram of Read Data Capture...
  • Page 397 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3 I/O DISCRIPTION Function Signal Description Type DDR2SEL Memory Type Selection XDDR2SEL dedicated (0; LPDDR1, 1: DDR2, LPDDR2) Memory Chip Select dedicated DDR_CSn[1:0] Xm1CSn[1:0] Memory Clock Xm1SCLK dedicated DDR_SCLK nSCLK Memory Negative Clock Xm1nSCLK...
  • Page 398 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 3.1 PAD MUX FOR DRAM TYPE mDDR LPDDR2 DDR2 PAD Name 64MB 128MB 256MB 256MB 64MB 128MB 256MB 512MB Xm1ADDR[0] ADDR_0 ADDR_0 ADDR_0 CA_0 ADDR_0 ADDR_0 ADDR_0 ADDR_0 ADDR_0 Xm1ADDR[1] ADDR_1 ADDR_1 ADDR_1 CA_1...
  • Page 399 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 REGISTER DESCRIPTION 4.1 REGISTER OVERVIEW Register Address Description Reset Value CONCONTROL 0xE600_0000 Controller Control Register 0x0FFF1310 MEMCONTROL 0xE600_0004 Memory Control Register 0x00202100 MEMCONFIG0 0xE600_0008 Memory Chip0 Configuration Register 0x20F80312 MEMCONFIG1 0xE600_000C Memory Chip1 Configuration Register...
  • Page 400 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2 DETAILED DESCRIPTION 4.2.1 Controller Control Register (ConControl, R/W, Address=0xE600_0000) Reset CONCONTROL Description Value Reserved [31:28] Should be zero Default Timeout Cycles 0xn = n aclk cycles (aclk: AXI clock) This counter prevents transactions in command queue from starvation.
  • Page 401 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Reset CONCONTROL Description Value Read Cycle Gap for Two Different Chips 0x0 = Disable, 0x1 = Enable ctc_rtr_gap_en To prevent collision between reads from two different memory devices, a one-cycle gap is required. Enable this register to insert the gap automatically for continuous reads from two different memory devices.
  • Page 402 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.2 Memory Control Register (MemControl, R/W, Address=0xE600_0004) Reset MEMCONTROL Description Value Reserved [31:23] Should be zero Memory Burst Length 0x0 = Reserved, 0x1 = 2, 0x2 = 4, [22:20] 0x3 = 8, 0x4 = 16,...
  • Page 403 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Reset MEMCONTROL Description Value mclk cycles to wait until timeout precharge precharges the open bank. Refer to “Section 2.4.2. Timeout Precharge”. Type of Dynamic Power Down 0x0 = Active/ Precharge power down, dpwrdn_type [3:2]...
  • Page 404 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.3 Memory Chip0 Configuration Register (MemConfig0, R/W, Address=0xE600_0008) Reset MEMCONFIG0 Description Value AXI Base Address AXI base address [31:24] = chip_base, chip_base [31:24] 0x20 For example, if chip_base = 0x20, then AXI base address of memory chip0 becomes 0x2000_0000.
  • Page 405 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.4 Memory Chip1 Configuration Register (MemConfig1, R/W, Address=0xE600_000C) Reset MEMCONFIG1 Description Value AXI Base Address AXI base address [31:24] = chip_base, chip_base [31:24] 0x28 For example, if chip_base = 0x28, then AXI base address of chip1 becomes 0x2800_0000.
  • Page 406 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.5 Memory Direct Command Register (DirectCmd, R/W, Address=0xE600_0010) Reset DIRECTCMD Description Value Reserved [31:28] Should be zero. Type of Direct Command 0x0 = MRS/EMRS (mode register setting), 0x1 = PALL (all banks precharge), 0x2 = PRE (per bank precharge),...
  • Page 407 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.6 Precharge Policy Configuration Register (PrechConfig, R/W, Address=0xE600_0014) Reset PRECHCONFIG Description Value Timeout Precharge Cycles 0xn = n mclk cycles, If the timeout precharge function (MemControl.tp_en) is tp_cnt [31:24] 0xFF enabled and the timeout precharge counter becomes zero, the controller forces the activated memory bank into the precharged state.
  • Page 408 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.7 PHY Control0 Register (PhyControl0, R/W, Address=0xE600_0018) Reset PHYCONTROL0 Description Value DLL Force Delay This field is used instead of ctrl_lock_value[9:2] from the DLL ctrl_force [31:24] when ctrl_dll_on is LOW. (i.e. If the DLL is off, this field is used to generate 270' clock and shift DQS by 90'.)
  • Page 409 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) NOTE PHY DLL Lock Procedure. Power up & Memory DLL Lock Memory Acess PLL lock Initialization rst_n Write ctrl_start_point value ctrl_start_point Write ctrl_inc value ctrl_inc DLL Lock Start ctrl_start DLL Locked ctrl_clock ctrl_flock ctrl_lock_value...
  • Page 410 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.8 PHY Control1 Register (PhyControl1, R/W, Address=0xE600_001C) Reset PHYCONTROL1 Description Value dqs_delay [31:28] Delay Cycles for DQS Cleaning Reserved [27:23] Should be zero This field is for debug purpose. If this field is fixed, this should not be changed during operation.
  • Page 411 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Phase Delay for DQS Cleaning GATEout signal delay amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid after ctrl_resync becomes HIGH and LOW. 0x000 = T/128 (2.8125' shift), 0x001 = T/64 (5.625' shift),...
  • Page 412 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER tA: I/O output delay tB: Package bonding wire delay tC: Package board delay tD: Board trace delay tE: I/O input delay tDL: delay line delay tAC: minimum CK-to-DQS timing of LPDDR/DDR2 memory spec. (LPDDR ( 1ns, DDR2 ( 0.5tCK) tFS : Fine step delay in DLL, From PhyStatus0.ctrl_lock_value[9:0], tFS can beis calculated.
  • Page 413 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) tAC (min ) {burst length }/2 {burst length } = 2, 4, 8, 16 ctrl _offsetc [6] = 1'b0 ctrl_offsetc [6:0] = 6'h0 T /8 tFS : Fine Step Delay T /8 + ( ctrl _offsetc [5:0] x tFS )
  • Page 414 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.9 PHY Control2 Register (PhyControl2, R/W, Address=0xE600_0020) Reset PHYCONTROL2 Description Value Reserved [31] Should be zero This field is for debug purpose. If this field is fixed, this should not be changed during operation. This value is valid after ctrl_resync becomes HIGH and LOW.
  • Page 415 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.10 Dynamic Power Down Configuration Register (PwrdnConfig, R/W, Address=0xE600_0028) Reset PWRDNCONFIG Description Value Number of Cycles for Dynamic Self Refresh Entry 0xn = n aclk cycles, dsref_cyc [31:16] 0xFFFF If the command queue is empty for n+1 cycles, the controller forces the memory device into self refresh state.
  • Page 416 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.11 AC Timing Register for Auto Refresh of memory (TimingAref, R/W, Address=0xE600_0030) Reset TIMINGAREF Description Value Reserved [31:16] Should be zero Average Periodic Refresh Interval Should be minimum. memory tREFI (all bank) < t_refi *...
  • Page 417 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.13 AC Timing Register for the Data of memory (TimingData, R/W, Address=0xE600_0038) Reset TIMINGDATA Description Value Internal write to Read command delay, in cycles t_wtr * T(mclk) should be greater than or equal to the minimum...
  • Page 418 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.14 AC Timing Register for the Power mode of Memory (TimingPower, R/W, Address=0xE600_003C) Reset TIMINGPOWER Description Value Reserved [31:30] Should be zero Four Active Window t_faw [29:24] t_faw * T(mclk) should be greater than or equal to the...
  • Page 419 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.15 PHY Status Register 0 (PhyStatus0, R, Address=0xE600_0040) Reset PHYSTATUS0 Description Value Reserved [31:14] Should be zero Locked Delay Locked delay line encoding value ctrl_lock_value [13:4] ctrl_lock_value[9:2]: number of delay cells for coarse lock...
  • Page 420 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.17 Memory Chip0 Status Register (Chip0Status, R, Address=0xE600_0048) Reset CHIP0STATUS Description Value bank7_state [31:28] The current state of bank 7 of memory chip0 bank6_state [27:24] The current state of bank 6 of memory chip0...
  • Page 421 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.18 Memory Chip1 Status Register (Chip1Status, R, Address=0xE600_004C) Reset CHIP1STATUS Description Value bank7_state [31:28] The current state of bank 7 of SDRAM chip1 bank6_state [27:24] The current state of bank 6 of SDRAM chip1...
  • Page 422 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.19 Counter Status Register for the Auto Refresh (ArefStatus, R, Address=0xE600_0050) Reset AREFSTATUS Description Value Reserved [31:16] Should be zero Current Value of Auto Refresh Counter Shows the current value of all bank auto refresh counter.
  • Page 423 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.22 PHY Test Register 1 (PhyTest1, R, Address=0xE600_005C) Reset PHYTEST1 Description Value ctrl_fb_cnt3 [31:24] Count value for data3 channel ctrl_fb_cnt2 [23:16] Count value for data2 channel ctrl_fb_cnt1 [15:8] Count value for data1 channel ctrl_fb_cnt0...
  • Page 424 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER 4.2.24 Quality of Service Configuration Register n (QosConfig n, R/W, Address=0xE600_0064 + 8n (n=0~7, integer) Reset QOSCONFIGn Description Value QoS Mask Bits This is used to mask the incoming ARID to compare with the qos_id.
  • Page 425 DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Table 5.1-1 Master Transaction ID in S5PC100 (1/2) Transaction Transaction ID Description Master 12'b0000_0000_0000 Integer data & NEON - Noncacheable or strongly ordered read/write 12'b0000_0000_0100 Integer data & NEON - Shared device read/ write 12'b0000_0000_1000 Integer data &...
  • Page 426 S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER Table 5.1-1 Master Transaction ID in S5PC100 (2/2) (Continued) Transaction Transaction ID Description Master 12'b0000_0000_0110 VP Y line buffer 0 12'b0000_0100_0110 VP Y line buffer 1 12'b0000_1000_0110 VP Y line buffer 2 12'b0000_1100_0110 VP Y line buffer 3...
  • Page 427: Static Memory Controller

    S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER STATIC MEMORY CONTROLLER 1 OVERVIEW The S5PC100 Static Memroy Controller supports external 8/ 16-bit NOR Flash/ PROM/ SRAM memory. From now on, we refer this controller as SMC. SMC supports 6-bank memory (Maximum 128MB). 1.1 FEATURE •...
  • Page 428 STATIC MEMORY CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.2 BLOCK DIAGRAM AHB I/F for SROM SFR SROM I/F SROM CONTROL & SINGAL SROM MEM I/F STATE MACHINE GENERATO DECODER AHB I/F for SROM MEM DATA PATH Figure 5.2-1 SMC Block Diagram...
  • Page 429 S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER 2 FUNCTIONAL DESCRIPTION SMC Controller support SMC interface for Bank0 to Bank5. 2.1 NWAIT PIN OPERATION If the WAIT corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active.
  • Page 430 STATIC MEMORY CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.2 PROGRAMMABLE ACCESS CYCLE HCLK ADDR ADDRESS 0 ADDRESS 1 Tcah Tacs nGCS Tcoh Tcos Tacc Tacp DATA(R) DATA 0 DATA 1 Tacs = 2-cycle Tacp = 2-cycle Tcos = 2-cycle Tcoh = 2-cycle...
  • Page 431 S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER 3 I/O DESCRIPTION Function Signal Description Type SMC_nCS[5:0] Output Bank Selection Signal Xm0CSn[5:0] muxed SMC_ADDR[20:0] Output Address bus Xm0ADDR[20:0] muxed SMC_OEn Output Output Enable Xm0OEn muxed SMC_WEn Output Write Enable Xm0WEn muxed SMC_Ben [1:0]...
  • Page 432 STATIC MEMORY CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 REGISTER DESCRIPTION Register Address Description Reset Value SMC_BW 0xE700_0000 SMC Bus Width & Wait control 0x00000009 SMC_BC0 0xE700_0004 SMC Bank0 Control Register 0x000F0000 SMC_BC1 0xE700_0008 SMC Bank1 Control Register 0x000F0000 SMC_BC2 0xE700_000C...
  • Page 433 S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER 4.1 SMC BUS WIDTH & WAIT CONTRL REGISTER (SMC_BW, RW, ADDRESS=0XE700_0000) Field Description Reset Value Reserved [31:24] Reserved nWBE / nBE(for UB/LB) control for Memory Bank5 ByteEnable5 [23] 0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
  • Page 434 STATIC MEMORY CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Field Description Reset Value Select SMC ADDR Base for Memory Bank3 0 = SMC_ADDR is Half-word base address. (SRAM_ADDR[20:0] ← HADDR[21:1]) AddrMode3 [13] 1 = SMC_ADDR is byte base address (SMC_ADDR[20:0] ← HADDR[20:0]) Note: If DataWidth0 is “0”, SMC_ADDR is byte base address.
  • Page 435 S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER Field Description Reset Value nWBE / nBE(for UB/LB) control for Memory Bank0 ByteEnable0 0 = UB/LB used (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = UB/LB not used (XrnWBE[1:0] is dedicated nBE[1:0] Wait enable control for Memory Bank0...
  • Page 436 STATIC MEMORY CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2 SMC BANK CONTROL REGISTER (SMC_BC: XRCSN0 ~ XRCSN2) Register Address Description Reset Value SMC_BC0 0xE700_0004 SMC Bank0 Control Register 0x000F0000 SMC_BC1 0xE700_0008 SMC Bank1 Control Register 0x000F0000 SMC_BC2 0xE700_000C SMC Bank2 Control Register...
  • Page 437 S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER Field Description Reset Value Address holding time after nGCSn 0000 = 0 clock 0001 = 1 clocks 0010 = 2 clocks 0011 = 3 clocks Tcah [11:8] …………. 0000 1100 = 12 clocks...
  • Page 438 ONENAND CONTROLLER 1 OVERVIEW S5PC100 supports external 16-bit bus for both asynchronous and synchronous OneNAND external memory via shared memory port 0. The controller is a complete embedded controller that interfaces directly to Input/ Output (I/O) drivers in the I/O pad ring that connect to OneNAND Flash memory devices.
  • Page 439 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.2 CONTROLLER USAGE EXPECTATIONS The controller is designed with the following expectations: • If the controller is in “Spare area” mode or “Main + Spare area” mode (set through the programming of the TRANS_SPARE parameter and the command type used), programming the memory burst length value to 32 causes an unsupported command interrupt.
  • Page 440 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 2 FUNCTIONAL DESCRIPTION 2.1 BLOCK DIAGRAM Figure 5.3-1 OneNAND Controller Block Diagram 2.2 CLOCK CONTROL The controller has three clock source inputs. Bus system interface gets AHB bus clock, HCLK. Flash controller core gets two flash clocks, SCLK_ONENAND and SCLK_ONENAND2. Frequency of SCLK_ONENAND should be double of SCLK_ONENAND2, which is supplied to OneNAND flash memory.
  • Page 441 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1. Ensure that there are no memory transfers. 2. Switch the clock ratio in the SFR of Clock Controller. 3. Write to the Clock Ratio Register. 4. Start the memory accesses. 2.3 ACCESS CLOCKS...
  • Page 442 S5PC100 and to the memory devices is stable. The controller does not include circuitry to control the activation of power and ground to the system. Once the power to the memory devices and the S5PC100 is stable, the controller must be initialized.
  • Page 443 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.5 ADDRESS MAPPING There are four kinds of interfaces supported by the controller. These interfaces are selected through the value of bits 27 and 26 of the incoming address. The interface mapping determines the way how the lower 26 bits of the address bus are used.
  • Page 444 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER address of the read/ write is in the area of the part that is being erased, the controller holds off the read/ write until the erase is completed. OneNAND Flash memory devices contain ECC circuitry and data is checked against the expected check code on read commands.
  • Page 445 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Table 5.3-1 summarizes the MAP10 commands. 2.5.5 MAP11 The MAP11 interface is a direct interface with the memory device. Through this interface, you have direct control of the address specified without any translation through the controller. The address MAPused is dependent on the memory device being used.
  • Page 446 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER Table 5.3-1 MAP10 Commands Cmd Type Cmd Value[15:0] Function Write 0x0000 Save erase status to controller Read Send current or last erase status to AHB interface Write 0x0001 Save block address for multi-block erase...
  • Page 447 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Table 5.3-2 Address Mapping Addr MAP00 MAP11 MAP01 device ID; b0000 b0001 b0010 b0011 b0011 b0100 b0100 b0101 b0101 Density 128Mb 256Mb 512Mb 1Gb(D) 2Gb(D) 4Gb(D) CMD_MAP resv. resv. resv. resv. resv. resv. resv.
  • Page 448 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 2.6 WATCHDOG TIMER The watchdog state machine monitors the various state machines of the controller. If the watchdog state machine detects a potential hang in the controller or is waiting for some information from the OneNAND Flash memory device, it is send out a watchdog interrupt if the watchdog timer expires.
  • Page 449 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3 I/O DESCRIPTION Function Signal Description TYPE Data Bus outputs address during memory read/ write address phase, inputs data during memory read data OND_DATA[15:0] Xm0DATA[15:0] muxed phase and outputs data during memory write data phase.
  • Page 450 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4 REGISTER DESCRIPTION Register Address Description Reset Value MEM_CFG 0xE710_0000 Memory Device Configuration Register Device Dependent BURST_LEN 0xE710_0010 Burst Length Register Device Dependent MEM_RESET 0xE710_0020 Memory Reset Register 0x0000 INT_ERR_STAT 0xE710_0030 Interrupt Error Status Register...
  • Page 451 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value Reserved 0xE710_0240 Reserved 0x0000 Reserved 0xE710_0250 Reserved 0x0000 WTCHDG_RST_L 0xE710_0260 Programmable Watchdog Delay 0x21c0 Counter Register WTCHDG_RST_H 0xE710_0270 Programmable Watchdog Delay 0x000d Counter Register SYNC_WRITE 0xE710_0280 Synchronous Write Enable Register...
  • Page 452 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.1 MEMORY DEVICE CONFIGURATION REGISTER (MEM_CFG, R/W, ADDRESS = 0XE710_0000) MEM_CFG0 Description Reset Value Reserved [31:16] Reserved The value programmed depends on the actual memory device being used. This data is used to configure the flash device for...
  • Page 453 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.4 INTERRUPT ERROR STATUS REGISTER (INT_ERR_STAT, R/W, ADDRESS = 0XE710_0030) INT_ERR_STAT Description Reset Value Reserved [31:14] Reserved An error occurred during a cache read or write setup or operation. If the host does not send an appropriate sequence of MAP01 following a MAP10 pipeline command, then the controller issues a Cache_Op_Err.
  • Page 454 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.5 INTERRUPT ERROR MASK REGISTER (INT_ERR_MASK, R/W, ADDRESS = 0XE710_0040) INT_ERR_MASK Description Reset Value Reserved [31:14] Reserved Cache_Op_Err [13] Rst_Cmp [12] Reserved [11] INT_act [10] Unsup_Cmd Mask bits that correspond to the bits in the int_error_status Locked_Blk register.
  • Page 455 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.7 ECC ERROR STATUS REGISTER (ECC_ERR_STAT_1, R, ADDRESS = 0XE710_0060) ECC_ERR_STAT_1 Description Reset Value Reserved [31:16] Reserved Memory Device The value programmed depends on the actual memory device Device [15:0] Dependent being used. This data is used to report ECC error information.
  • Page 456 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.11 BOOT BUFFER SIZE REGISTER (BOOT_BUF_SIZE, R, ADDRESS = 0XE710_00A0) BOOT_BUF_SIZE Description Reset Value Reserved [31:16] Reserved The value programmed depends on the actual memory device Memory Device Device [15:0] being used. This register is set by the controller after reset.
  • Page 457 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.16 FSA WIDTH REGISTER (FSA_WIDTH, R/W, ADDRESS = 0XE710_00F0) FSA_WIDTH Description Reset Value Reserved [31:3] Reserved Sets the number of bits used to represent the number of Device [2:0] sectors. The default value is 0x2. Set by software during Dependent initialization.
  • Page 458 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.19 TRANSFER SIZE REGISTER (TRANS_SPARE, R/W, ADDRESS = 0XE710_0140) TRANS_SPARE Description Reset Value Reserved [31:1] Reserved If this bit is set, the data in the spare area of memory is transferred to the asynchronous FIFO of the controller along with the main data.
  • Page 459 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.23 INTERRUPT PIN ENABLE REGISTER (INT_PIN_ENABLE, R/W, ADDRESS = 0XE710_01A0) INT_PIN_ENABLE Description Reset Value Reserved [31:1] Reserved Interrupt Pin Enable. Enables interrupt information to be transmitted to the host. An interrupt is only sent to the host if a bit is set in the int_error_status register, the corresponding bit is set in the INT_ERR_MASK register AND this bit is set.
  • Page 460 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.27 FLASH VERSION ID REGISTER (FLASH_VER_ID, R, ADDRESS = 0XE710_01F0) FLASH_VER_ID Description Reset Value Reserved [31:16] Reserved The value programmed depends on the actual memory device Memory Device Device [15:0] being used. This register is set by the controller after reset.
  • Page 461 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.32 SYNCHRONOUS WRITE ENABLE REGISTER (SYNC_WRITE, R, ADDRESS = 0XE710_0280) SYNC_WRITE Description Reset Value Reserved [31:1] Reserved Synchronous write enable. Set by software during initialization. If this bit is not set, the controller assumes that the device connected does not support synchronous writes.
  • Page 462 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.34 COLD RESET DELAY ENABLE REGISTER (COLD_RST_DLY, R/W, ADDRESS = 0XE710_02A0) COLD_RST_DLY Description Reset Value Reserved [31:15] Reserved Defines the value for cold reset delay. After a cold reset, the Cold_Reset_Delay [14:0] The controller waits for this number of cycles before reading 0x3355 the device registers.
  • Page 463 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.39 DEVICE STATUS REGISTER (DEV_STAT, R, ADDRESS = 0XE710_02F0) DEV_STAT Description Reset Value Reserved [31:16] Reserved Holds the status register information from the device that was Status [15:0] last read. Read-Only. 4.40 ECC ERROR STATUS REGISTER 2 (ECC_ERR_STAT_2, R, ADDRESS = 0XE710_0300)
  • Page 464 S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER 4.44 DEVICE PAGE SIZE ENABEL REGISTER (DEV_PAGE_SIZE, R/W, ADDRESS = 0XE710_0340) DEV_PAGE_SIZE Description Reset Value Reserved [31:2] Reserved Size of a single page of the device. Device Page Size [1:0] 00 = 1 KB; 01 = 2 KB; 10 = 4 KB; 11 = 8 KB 4.45 SUPERLOAD SUPPORT REGISTER (SUPERLOAD_EN, R/W, ADDRESS = 0XE710_0350)
  • Page 465 ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.49 INT MON STATUS (INT_MON_STATUS, R, ADDRESS = 0XE710_0390) INT_MON_STAT Description Reset Value Reserved [31:6] Reserved 6’h0; RESET WAIT int_mon_status [5:0] 6’h1; IDLE 6’h2 … 6’h35 are dependent on H/W. 5.3-28...
  • Page 466 DRAM. S5PC100 boot code is executed on an external NAND Flash memory. The boot code copies NAND Flash content to DRAM. The hardware ECC is used to check data validity of the NAND Flash. After the NAND Fash content is copied to DRAM, main program is executed on DRAM.
  • Page 467 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.1 BLOCK DIAGRAM nFCE ECC Gen. NAND FLASH Interface Slave I/F Control & R/nB State Machine I/O0 - I/O7 Figure 5.4-1 NAND Flash Controller Block Diagram 2.2 NAND FLASH MEMORY TIMING TACLS TWRPH0...
  • Page 468 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER TWRPH0 TWRPH1 HCLK nWE / nRE DATA DATA Figure 5.4-3 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) 5.4-3...
  • Page 469 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3 SOFTWARE MODE S5PC100 only supports software mode access. Use this mode to access NAND flash memory completely. The NAND Flash Controller supports direct access interface with the NAND flash memory. • Writing to the command register (NFCMMD) = the NAND Flash Memory command cycle •...
  • Page 470 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 4 DATA REGISTER CONFIGURATION 1) 8-bit NAND Flash Memory Interface A. Word Access Register Endian Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0] NFDATA Little I/O[ 7:0] I/O[ 7:0] I/O[ 7:0] I/O[ 7:0] B.
  • Page 471 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5 1-BIT/ 4-BIT/ 8-BIT ECC (ERROR CORRECTION CODE) NAND Flash controller has four Error Correction Code (ECC) modules for 1-bit ECC, one ECC module for 4-bit ECC and one for 8-bit ECC. For 1-bit ECC, NAND Flash controller has 4 ECC modules. Some 1-bit ECC modules are used to generate (up to) 2048 bytes ECC parity code and the others are used to generate (up to) 4 bytes ECC Parity code.
  • Page 472 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 5.3 1-BIT ECC MODULE FEATURES Generation of 1-bit ECC is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. If ECCLock is Low, H/W ECC modules generate ECC codes. 1-bit ECC Register Configuration Following tables shows the configuration of 1-bit ECC value read from spare area of external NAND Flash memory.
  • Page 473 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.4 1-BIT ECC PROGRAMMING GUIDE 1. To use SLC ECC in software mode, reset the ECCType to ‘0’ (enable SLC ECC)‘. ECC module generates ECC parity code for all read/ write data if MainECCLock (NFCON[7]) and SpareECCLock (NFCON[6]) are unlocked(‘0’).
  • Page 474 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 5.5 4-BIT ECC PROGRAMMING GUIDE (ENCODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and set the ECCType to “10” (enable 4bit ECC). The ECC module generates ECC parity code for 512-byte write data. You must reset the ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’...
  • Page 475 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.6 4-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 4-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and set the ECCType to “10” (enable 4bit ECC). ECC module generates ECC parity code for 512-byte read data. Therefore write the InitMECC (NFCONT[5]) bit as ‘1’...
  • Page 476 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 5.7 8-BIT ECC PROGRAMMING GUIDE (ENCODING) 1. To use 8-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and set the ECCType to “01” (enable 8-bit ECC). The ECC module generates ECC parity code for 512-byte write data. Therefore reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’...
  • Page 477 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.8 8-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 8-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and set the ECCType to “01” (enable 8bit ECC). The ECC module generates ECC parity code for 512-byte read data. Therefore reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’...
  • Page 478 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 6 I/O DESCRIPTION Function Signal Description Type NF_DATA[15:0] Input / Output Address/ Data Bus Xm0DATA muxed NF_RnB[3:0] Input Ready and Busy Xm0FRnB muxed NF_CLE Output Command Latch Enable Xm0FCLE muxed NF_ALE Output Address Latch Enable...
  • Page 479 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7 REGISTER DESCRIPTION Register Address Description Reset Value NFCONF 0xE720_0000 Configuration Register 0xX000100X NFCONT 0xE720_0004 Control Register 0x000100C6 NFCMMD 0xE720_0008 Command Register 0x00000000 NFADDR 0xE720_000C Address Register 0x00000000 NFDATA 0xE720_0010 Data Register 0x00000000...
  • Page 480 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.1 NAND FLASH CONFIGURATION REGISTER (NFCONF, R/W, ADDRESS = 0XE720_0000) NFCONF Description Reset Value Reserved [31] Reserved MLCClkCtrl [30] Clock control for 4-bit ECC & 8-bit ECC engine. 0: Recommended when system clock is more than 66MHz.
  • Page 481 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.2 CONTROL REGISTER (NFCONT, R/W, ADDRESS = 0XE720_0004) NFCONT Description Reset Value Reserved [31:24] Reserved NAND Flash Memory nRCS[3] signal control Reg_nCE3 [23] 0 = Force nRCS[3] to low (Enable chip select) 1 = Force nRCS[3] to High (Disable chip select)
  • Page 482 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER NFCONT Description Reset Value 1 = Enables interrupt MLCStop [11] 8-bit ECC encoding/ decoding operation initialization Illegal access interrupt control 0 = Disables interrupt 1 = Enables interrupt EnbIllegalAccINT [10] Illegal access interrupt occurs if CPU tries to program or erase locking area (the area setting in NFSBLK (0xE720_0020) to NFEBLK (0xE720_0024)-1.
  • Page 483 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.3 COMMAND REGISTER (NFCMMD, R/W, ADDRESS = 0XE720_0008) NFCMMD Description Reset Value Reserved [31:8] Reserved 0x000000 REG_CMMD [7:0] NAND Flash memory command value 0x00 7.4 ADDRESS REGISTER (NFADDR, R/W, ADDRESS = 0XE720_000C) NFADDR...
  • Page 484 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.7 MAIN DATA AREA ECC REGISTER (NFMECCD0, R/W, ADDRESS = 0XE720_0018) NFMECCD1 Description Reset Value ECCData3_1 [31:24] 0x00 ECC for I/O[15:8] ECCData3_0 [23:16] 0x00 ECC for I/O[ 7:0] (ECC3) ECCData2_1 [15:8] 0x00 ECC for I/O[15:8]...
  • Page 485 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.9 PROGRMMABLE BLOCK ADDRESS REGISTER (NFSBLK, R/W, ADDRESS = 0XE720_0020) NFSBLK Description Reset Value Reserved [31:24] Reserved 0x00 SBLK_ADDR2 [23:16] The 3 block address of the block erase operation 0x00 SBLK_ADDR1 [15:8] The 2...
  • Page 486 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.11 NFCON STATUS REGISTER (NFSTAT, R/W, ADDRESS = 0XE720_0028) NFSTAT Description Reset Value The status of RnB[3:0] input pin. Flash_RnB_GRP [31:28] 0 = NAND Flash memory busy 1 = NAND Flash memory ready to operate If RnB[3:0] low to high transition is occurs, this field is set.
  • Page 487 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.12 ECC0/1 ERROR STATUS REGISTER (NFECCERR0, R, ADDRESS = 0XE720_002C) • If ECCType is 1bit ECC NFECCERR0 Description Reset Value Reserved [31:25] Reserved 0x00 ECC0SDataAddr [24:21] In spare area, Indicates which number data has error...
  • Page 488 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.13 ECC0/1 ERROR STATUS REGISTER (NFECCERR1, R, 0XE720_0030) • If ECCType is 1bit ECC NFECCERR1 Description Reset Value Reserved [31:25] Reserved 0x00 ECC1SDataAddr [24:21] In spare area, Indicates which number data has error...
  • Page 489 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.14 MAIN DATA AREA ECC0 STATUS REGISTER (NFMECC0, R, ADDRESS = 0XE720_0034) • If ECCType is 1 bit ECC. NFMECC0 Description Reset Value MECC0_3 [31:24] ECC3 for data[7:0] 0xFF MECC0_2 [23:16] ECC2 for data[7:0]...
  • Page 490 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.15 MAIN DATA AREA ECC0 STATUS REGISTER (NFMECC1, R, ADDRESS = 0XE720_0038) • If ECCType is 1 bit ECC. NFMECC1 Description Reset Value MECC1_3 [31:24] ECC3 data[15:8] 0xFF MECC1_2 [23:16] ECC2 data[15:8] 0xFF...
  • Page 491 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.16 SPARE AREA ECC STATUS REGISTER (NFSECC, R, ADDRESS = 0XE720_003C) NFSECC Description Reset Value SECC1_1 [31:24] Spare area ECC1 Status for I/O[15:8] 0x03 SECC1_0 [23:16] Spare area ECC0 Status for I/O[15:8] 0xFF...
  • Page 492 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.18 ECC0/1/2 FOR 8BIT ECC STATUS REGISTER (NFECCERR0, R, ADDRESS = 0XE720_0044) NFECCERR0 Description Reset Value Indicates that the 8-bit ECC decoding engine is searching whether a error exists or not MLC8ECCBusy [31]...
  • Page 493 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.20 ECC0/1/2 FOR 8BIT ECC STATUS REGISTER (NFECCERR1, R, ADDRESS = 0XE720_004C) NFECCERR1 Description Reset Value MLCErrLocation8 [31:22] 0x000 Error byte location of 8 bit error Reserved [21] Reserved MLCErrLocation7 [20:11] Error byte location of 7...
  • Page 494 S5PC100 USER’S MANUAL (REV1.0) NAND FLASH CONTROLLER 7.21 MAIN DATA AREA ECC0 STATUS REGISTER (NFM8ECC0, R, ADDRESS = 0XE720_0050) NFM8ECC0 Description Reset Value Parity [31:24] Check Parity generated from main area (512-byte) 0x00 Parity [23:16] Check Parity generated from main area (512-byte)
  • Page 495 NAND FLASH CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.25 MLC 8-BIT ECC ERROR PATTEN REGISTER (NFMLC8BITPT0, R, ADDRESS = 0XE720_0060) NFMLC8BITPT0 Description Reset Value [31:24] 0x00 Error bit pattern Error bit pattern Error bit pattern [23:16] Error bit pattern 0x00 Error bit pattern...
  • Page 496 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER COMPACT FLASH CONTROLLER 1 OVERVIEW A Compact Flash Controller (CFC) connects seamlessly to the AHB Bus as a Bus slave and AHB Master. The CFC Subsystem recognizes AHB Bus transactions that target the compact flash card. The Master Interface initiates compact flash card requests to the CFC block requester interface .
  • Page 497 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.2 BLOCK DIAGRAM CF controller AHB master IF ATAPI controller CF card AHB slave IF PC card controller IDE mode HADDR Output pad enble Address Top level SFR Card power enable decoder Figure 5.5-1 CFC Block Diagram...
  • Page 498 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 1.3 FUNCTIONAL DESCRIPTION PC Card using memory mode has two distinct memory spaces namely: Attribute memory and Common memory. The Attribute memory holds descriptive information and configuration registers (Card Information Structure CIS). CIS informs about the type of card inserted and is used to configure system to recognize different types of cards and load the correct drivers.
  • Page 499 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.4 PC CARD MODE TIMING DIAGRAM The Figure 5.5-6, Figure 5.5-7, Figure 5.5-8 and Figure 5.5-9 shows the timing diagrams in the PC Card mode. nCE1 nCE2 IORD IOWR IDLE SET UP COMMAND HOLD IDLE Figure 5.5-2 PC Card State Definition...
  • Page 500 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER HCLK HTRANS HADDR 0x20 0x22 0x24 HREADY HWDATA Data(0x20) Data(0x22) HRDATA Data(0x20) Data(0x22) IDLE SETUP COMMAND HOLD IDLE SETUP COMMAND HOLD IDLE ADDR[25:0] 0x20 0x22 CE1# CE2# REG# I/ O IORD# interface IOWR# Memory...
  • Page 501 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) The PC card mode operation has four states namely: IDLE, SETUP, COMMAND, and HOLD. The timing for various states is set in special function registers: PCCARD_ATTR, PCCARD_I/O AND PCCARD_COMM. Each register contains timing for SETUP, COMMAND and HOLD state for the attribute, I/O or common memory.
  • Page 502 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 1.5 TRUE IDE MODE PIO/ PDMA TIMING DIAGRAM The PIO transfer protocol supports 8-bit register access in driver and 16-bit PIO data access. Both hosts and devices support ATA_IORDY if PIO mode 3 or 4 is the currently selected mode of operation. The Figure 5.5-6 defines the relationships between host and device interface signals for data and registers transfer.
  • Page 503 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Table 5.5-3 Timing Parameter Each PIO Mode Register Transfer MODE0 MODE1 MODE2 MODE3 MODE4 (70, --) (50, --) (30, --) (30, --) (25, --) (290, --) (290, --) (290, --) (80, --) (70, --)
  • Page 504 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 1.6 FLOWCHART FOR PIO READ / WRITE ATA_PIO_SCR register configure to 8'h00 ATA_PIO_LLR, ATA_PIO_LMR, ATA_PIO_LHR set to 8'hFF PIO timing register configured ATA_CONTROL register sets ATA enable ATA class set to PIO DMA transfer direction set...
  • Page 505 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.7 TRUE IDE MDMA MODE TIMING DIAGRAM The ATAPI MDMA streams data continuously across the ATA interface between the host and the target device. This transfer class allows either the driver or host to pause or terminate the data flow. To support various transfer speed classes, the CPU programs appropriate timing parameters.
  • Page 506 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 1.7.1 ATA_MDMA_TIME Register Setting Example The “td” minimum time is 215ns in the system clock is 100MHz (10ns). It gives 21.5; “td” divided by 10ns. This case has residual, assigning quotient (21) to the dma_td[3:0]. If it has no residual, assign the quotient minus 1 at dma_td[3:0].
  • Page 507 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.8 TRUE IDE UDMA MODE TIMING DIAGRAM The Ultra-DMA (UDMA) is a fast DMA protocol which supports six timing modes (mode 0 ~ 5). Mode 5 is the fastest; it operates at 100MHz. This ATAPI host controller supports to mode 4. It runs 66MHz. Both host and device driver perform CRC check during UDMA burst transfer.
  • Page 508 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER DMARQ DMACK DIOW DIOR tACKENV tACKENV CS0,CS1, DA[2:0] IORDY tDVS tDVH DD[15:0 ] or DD[7:0] Figure 5.5-10 UDMA - In Operation (Terminated by Host) DMARQ DMACK tACKENV tACKENV DIOW DIOR tACKENV CS0,CS1, DA[2:0] IORDY...
  • Page 509 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) DMARQ DMACK DIOW tACKENV DIOR CS0,CS1, DA[2:0] IORDY tDVS tDVH DD[15:0 ] or DD[7:0] Figure 5.5-12 UDMA - Out Operation (Terminated by Host) Table 5.5-5 Timing Parameter Each UDMA Mode UDMA mode UDMA 0...
  • Page 510 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 1.8.1 ATA_UDMA_TIME Register Setting Example The “tackenv” minimum time is 20ns in the system clock of 100MHz (10ns). It gives 2; “tackenv” divided by 10ns. This case has no residual, therefore the udma_tackenv[3:0] assigns 1 which is 2 minus 1. If it has residual, assign the quotient at udma_tackenv[3:0].
  • Page 511 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.9 TRANSFER STATE ABORT The PIO, PDMA, MDMA or UDMA checks for abort or stop transfer state after completing one full cycle of the finite state machine. The FSM transition from IDLE state happens if ATA transfer state is in ATA_TRANS. The FSM continues the cycle while the abort is asserted.
  • Page 512 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 1.10 EBI BACKOFF SUPPORTED PROTOCOL In the UDMA/ MDMA Class (True IDE mode), Device I/F can used with EBI (External BUS Interface) MUX; In this case, if the EBIBACKOFF signal is issued (by the higher priority controller), CFCON terminates the current transfer (unit is sector) as soon as possible.
  • Page 513 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.11 PROGRAMMER’S MODEL For top-level control and configuration of the CFC, use following register: 1. MUX_REG: Set internal mode and card power enable For configuration and status of PC Card mode, use following registers: 1.
  • Page 514 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 23. ATA_PIO_LLR: ATA PIO device LBA low register 24. ATA_PIO_LMR: ATA PIO device LBA middle register 25. ATA_PIO_LHR: ATA PIO device LBA high register 26. ATA_PIO_DVR: ATA PIO device register 27. ATA_PIO_CSD: ATA PIO device command/ status register 28.
  • Page 515 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 1.12 MEMORY MAP SFR_Base = SFR Area CFCON_Base + 0x1800 Common Memory Area CFCON_Base + 0x1000 I/O Area CFCON_Base + 0x0800 Attribute Memory Area CFCON_Base + 0x0000 Reserved Area SFR_Base + 0x0188 ATAPI controlller...
  • Page 516 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 2 PROGRAMMING GUIDE 2.1 BASIC DRAWING FUNCTION Start Card insert Interrupt request From PC card controller Internal mode setting 0 : PC card mode 1 : True-IDE mode True-IDE mode ? Output port enable...
  • Page 517 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.2 MISC 2.2.1 nCSEL The nCSEL is card selection pin. This signal internally pulled-up in CF/CF+ card. This configures the device as a Master or a Slave if configured in the True-IDE mode. If this pin is grounded, this device is configured as a Master.
  • Page 518 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 3 EXAMPLE CODES This explains the basic steps followed in the programming of the PCCARD MODE and ATA MODE. 3.1 INITIALIZATION ROUTINE PCCARD MODE:- void activate_cfc_controller (void) { apbif_single_write (CFC_PROGRAMMING, MUX_REG, 0xaaaa_aaa6); // Initialize the internal mode Register apbif_single_write (CFC_PROGRAMMING, PCCARD_CFNG_STATUS, 0xaaaa_00a0);...
  • Page 519 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.2 INTERRUPT SERVICE ROUTINE PCCARD MODE:- Void interrupt_service_routine ( void ) { //Poll for the INTSRC_ERR_N bit to be set to 0 in the PCCARD_INTMSK_SRC register wait_for_cfc_intstat(); //Read the INTSRC_ERR_N bit of the PCCARD_INTMSK_SRC register apbif_single_read (SEND_FROM_CFC, PCCARD_INTMSK_SRC);...
  • Page 520 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER apbif_single_write (SEND_TO_CFC, ATA_IRQ, 0Xaaaa_aff8); Void interrupt_service_routine ( void ) { //Poll for the atadev_irq_int bit to be set to 0 in the ATA_IRQ register wait_for_cfc_intstat(); //Read the atadev_irq_int bit of the ATA_IRQ register apbif_single_read (SEND_FROM_CFC, ATA_IRQ);...
  • Page 521 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 I/O DESCRIPTION Funtion Signal Description Type EBI muxed Indep. ATA CF_nCS[0] Card Enable Strobe, muxed Xm0CSn[4] XmsmCSn muxed with CF_CSn_0 CF_nCS[1] Card Enable Strobe, muxed Xm0CSn[5] XmsmWEn muxed with CF_CSn_1 CF_A [10:3] CF Card Address...
  • Page 522 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 4.1 ATA 40 PIN CONNECTOR Name Description Function Signal /RESET Reset CF_RESET Ground Data 7 CF_D[7] Data 8 CF_D[8] Data 6 CF_D[6] Data 9 CF_D[9] Data 5 CF_D[5] DD10 Data 10 CF_D[10] Data 4...
  • Page 523 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2 CF 50 PIN CONNECTOR Name Description Function Signal Ground Data 3 CF_D[3] Data 4 CF_D[4] Data 5 CF_D[5] Data 6 CF_D[6] Data 7 CF_D[7] -CE1 Card Enable 1 CF_nCS[0] Address 10 CF_A[10] Output Enable...
  • Page 524 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER Data 9 CF_D[9] Data 10 CF_D[10] Ground 5.5-29...
  • Page 525 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5 REGISTER DESCRIPTION 5.1 REGISTER OVERVIEW Register Address Description Reset Value CF card host controller base address MUX_REG 0xE780_1800 R/W Top control and configuration 0x00000002 Reserved ~ 0xE780_181C Reserved area PC card controller base address...
  • Page 526 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER Register Address Description Reset Value ATA_SBUF_SIZE 0xE780_1948 R/W ATA size of source buffer 0x00000000 ATA_CADR_TBUF 0xE780_194C ATA current write address of track buffer 0x00000000 ATA_CADR_SBUF 0xE780_1950 ATA current read address of source buffer 0x00000000...
  • Page 527 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2 DETAILED DESCRIPTION 5.2.1 Top Level Control and Configuration Register (MUX_REG, R/W, Address = 0xE780_1800) MUX_REG Description Initial State Reserved [31:3] Reserved Indep. ATA I/F Select. ATA_Indep_Port 0 = EBI Muxed port 1 = Indep. ATA I/F (Modem I/F)
  • Page 528 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.2 PC Card Configuration and Status Register (PCCARD_CNFG&STATUS, R/W, Address = 0xE780_1820 ) PCCARD_CNFG Description Initial State &STATUS Reserved [31:14] Reserved CF card reset in PC card mode CARD_RESET [13] 0 = No reset...
  • Page 529 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.3 Interrupt Source & Mask Register (PCCCARD_INTMASK&SRC, R/W, Address = 0xE780_1824) PCCCARD_INTMASK Description Initial State &SRC Reserved [31:11] Reserved Interrupt mask bit of no card error INTMSK_ERR_N [10] 0 = Unmask 1 = Mask...
  • Page 530 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.5 I/O Card Access Timing (PCCARD_I/O, R/W, Address = 0xE780_182C) PCCARD_I/O Description Reset Value Reserved [31:23] Reserved HOLD_IO [22:16] Hold state timing of I/O area 0x03 Reserved [15] Reserved CMND_IO [14:8] Command state timing of I/O area...
  • Page 531 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.8 ATA Status Register (ATA_STATUS, R, Address = 0xE780_1904) ATA_STATUS Description Reset Value Reserved [31:6] Reserved atadev_cblid ATAPI cable identification atadev_irq ATAPI interrupt signal line atadev_iordy ATAPI iordy signal line atadev_dmareq ATAPI dmareq signal line Transfer state 2’b00 = Idle state...
  • Page 532 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.9 ATA Command Register (ATA_COMMAND, R/W, Address = 0xE780_1908) ATA_COMMAND Description Reset Value Reserved [31:2] Reserved ATA transfer command Four command types (START, STOP, ABORT and CONTINUE) are supported for data transfer control. The “START”...
  • Page 533 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.10 ATA Software Reset (ATA_SWRST, R/W, Address = 0xE780_190C) ATA_SWRST Description Reset Value Reserved [31:1] Reserved Software reset for the ATAPI host 0 = No reset 1 = Resets device registers and all registers of ATAPI ata_swrst host controller except CPU interface registers.
  • Page 534 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.12 ATA Interrupt Mask Register (ATA_IRQ_MASK, R/W, Address = 0xE780_1914) ATA_IRQ_MASK Description Reset Value Reserved [31:10] Reserved 0 = Mask ebi_abort_rd_int; Disable mask_ebi_abort_rd_int 1 = Unmask ebi_abort_rd_int; Enable 0 = Mask ebi_abort_wr_int; Disable mask_ebi_abort_wr_int 1 = Unmask ebi_abort_wr_int;...
  • Page 535 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.13 ATA Configuration Register (ATA_CFG, R/W, Address = 0xE780_1918) ATA_CFG Description Reset Value Reserved [31] Reserved (This field should be 0x1) Reserved [30:13] Reserved Determines whether DMA is normal DMA dma_mode [12] 0 = ormal DMA mode 1 = Reserved.
  • Page 536 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.14 2 ATA Configuration for ATA Interface with EBI (ATA_CFG_2, R/W, Address = 0xE780_191C) ATA_CFG_2 Description Reset Value When support EBI BACKOFF, This value is used checked ebi_sc_end_value [31:24] that current transfer sector is done. (For DEBUGGING)
  • Page 537 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.15 ATA Multi_word DMA Timing (ATA_MDMA_TIME, R/W, Address = 0xE780_1928) ATA_MDMA_TIME Description Reset Value Reserved [31:20] Reserved dma_teoc [19:12] DMA timing parameter, Teoc, end of cycle time 0x2C dma_t2 [11:4] DMA timing parameter, tD, DIOR/DIOWn pulse width...
  • Page 538 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.18 ATA Transfer Count Number (ATA_XFR_NUM, R/W, Address = 0xE780_1934) ATA_XFR_NUM Description Reset Value Data transfer number. xfr_num [31:1] 0x00000000 To transfer 1-sector (512-byte), you should set 32’h1ff. Reserved Reserved 5.2.19 ATA Current Transfer Count (ATA_XFR_CNT, R, Address = 0xE780_1938)
  • Page 539 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.22 Start Address of the Source Buffer (ATA_SBUF_BASE, R/W, Address = 0xE780_1944) ATA_SBUF_BASE Description Reset Value src_buffer_base [31:2] Start address of source buffer (4byte unit) 0x00000000 Reserved [1:0] Reserved 5.2.23 Size of Source Buffer (ATA_SBUF_SIZE, R/W, Address = 0xE780_1948)
  • Page 540 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.26 ATA PIO Data Register (ATA_PIO_DTR, R/W, Address = 0xE780_1954) ATA_PIO_DTR Description Reset Value Reserved [31:16] Reserved pio_dev_dtr [15:0] 16-bit PIO data register 0x0000 5.2.27 ATA PIO Device Feature/Error Register (ATA_PIO_FED, R/W, Address = 0xE780_1958)
  • Page 541 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.31 ATA PIO Device LBA High Register (ATA_PIO_LHR, R/W, Address = 0xE780_1968) ATA_PIO_LHR Description Reset Value Reserved [31:8] Reserved pio_dev_lhr [7:0] 8-bit PIO LBA high (command block) register 0x00 5.2.32 ATA PIO Device Register (ATA_PIO_DVR, R/W, Address = 0xE780_196C)
  • Page 542 S5PC100 USER’S MANUAL (REV1.0) CF CONTROLLER 5.2.36 ATA PIO Read Data Register (ATA_PIO_RDATA, R, Address = 0xE780_197C) ATA_PIO_RDATA Description Reset Value Reserved [31:16] Reserved PIO read data register while HOST read from ATA pio_rdata [15:0] 0x0000 device register 5.2.37 AHB Bus FIFO Status Register (BUS_FIFO_STATUS, R, Address = 0xE780_1980)
  • Page 543 CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.38 ATA FIFO Status Register (ATA_FIFO_STATUS, R, Address = 0xE780_1984) ATA_FIFO_STATUS Description Reset Value Reserved [31] Reserved 0 = ATA_IDLE 1 = ATA_TRANS ata_state [30:28] 2 = ATA_PAUSE 0x0000 3 = ATA_PAUSE2 4 = ATA_ABORT 2’b00 = IDLE...
  • Page 544 EXTERNAL BUS INTERFACE OVERVIEW S5PC100 External Bus Interface (EBI), as a peripheral, relies on the memory controllers to release their external requests for the external bus when they are idle. Because it has no knowledge of when a transfer starts or completes.
  • Page 545 EXTERNAL BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) BLOCK DIAGRAM Figure 5.6-1 Memory Interface Through EBI 5.6-2...
  • Page 546 S5PC100 USER’S MANUAL (REV1.0) EXTERNAL BUS INTERFACE CLOCK SCHEME Figure 5.6-2 Clock Scheme of Memory Controllers and EBI NOTE: The OneNAND Clock selection register name in Chapter 02.03. Clock Controller is OneNAND_SEL (OneNAND_Async). This register address is 0xE010_0200 (CLK_SRC0[24]). 5.6-3...
  • Page 547 EXTERNAL BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) FUNCTIONAL DESCRIPTION Memory Subsystem can be configured by chapter 02.03. Clock controller. The memory configuration register name in System Controller is MEM_SYS_CFG. This register address is 0xE020_0200. Clock controller sends information based on fixed priority order. Fixed Priority Order is summarized in the table below: •...
  • Page 548 S5PC100 USER’S MANUAL (REV1.0) EXTERNAL BUS INTERFACE I/O DESCRIPTION Function Signal Description Type EBI_DATA_RDn Output Bank Selection Signal Xm0DATA_RDn muxed EBI I/O MUXING Function Signal Pad Name NFCON ONENANDC CFCON Xm0ADDR[20:0] SMC_ADDR[20:0] CF_A [10:0] Xm0DATA[15:0] SMC_DATA[15:0] NF_DATA[15:0] OND_DATA[15:0] CF_D[15:0] Xm0CSn[5:0]...
  • Page 549: Dma Controller

    DMA CONTROLLER 1 OVERVIEW S5PC100 supports 2 Direct Memory Access (DMA) tops, one for Memory to Memory (M2M) transfer (DMA_mem), and the other one for Peripheral to memory transfer and vice-versa (DMA_peri). The M2M DMA top consists of a PL330 and some logics. The Peri DMA top consists of two PL330s, and dma_map.
  • Page 550 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2 FEATURES Use the features listed in below table as reference for DMA and writing DMA assembly code. DMA_mem DMA_peri Supported Data Size Up-to double word (64-bit) Up-to word (32-bit) Word transfer: Up-to 8 burst...
  • Page 551 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Module DMA Request Category Service Module I2S0_RX IrDA UART3[1] UART3[0] UART2[1] System UART2[0] UART1[1] UART1[0] UART0[1] UART0[0] Peri DMA0 Reserved Reserved HSI_TX HSI_RX Others SPDIF by only DMA0 EXTERNAL (GPIO) AC_PCMout AC_PCMin AC_MICin SPI2_TX...
  • Page 552 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Module DMA Request Category Service Module UART3[1] UART3[0] UART2[1] UART2[0] UART1[1] UART1[0] UART0[1] UART0[0] SEC_TX DMA_mem Security by M2M DMA only SEC_RX 6.1-4...
  • Page 553 Most of the SFRs are read-only. The main role of SFR is to check the PL330 status. There are many SFRs for PL330, therefore we have explained S5PC100-specific SFR and related summary. For more information refer to “Chapter 3 of PL330 TRM”.
  • Page 554 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value 0xE810_0060- Reserved Reserved 0xE810_00FC Channel Status Registers. For more information refer to “Page 3-24 of PL330 TRM” 0xE810_0100 Channel Status for DMA Channel 0 0xE810_0108 Channel Status for DMA Channel 1...
  • Page 555 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Register Address Description Reset Value DA_5 0xE810_04A4 Destination Address for DMA Channel 5 DA_6 0xE810_04C4 Destination Address for DMA Channel 6 DA_7 0xE810_04E4 Destination Address for DMA Channel 7 Channel Control Registers. For more information refer to “Page 3-30 of PL330 TRM”...
  • Page 556 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value Reserved 0xE810_0474- Reserved 0xE810_047C Reserved 0xE810_0494- Reserved 0xE810_049C Reserved 0xE810_04B4- Reserved 0xE810_04BC Reserved 0xE810_04D4- Reserved 0xE810_04DC Reserved 0xE810_04F4- Reserved 0xE810_0CFC Debug Status Register. For more information refer DBGSTATUS 0xE810_0D00 to “Page 3-37 of PL330 TRM”...
  • Page 557 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Table 6.1-3 DMA_peri0 Register Summary Register Address Description Reset Value DMA Status Register. For more information refer to 0xE900_0000 “Page 3-11 of PL330 TRM” DMA Program Counter Register. For more 0xE900_0004 information refer to “Page 3-13 of PL330 TRM”...
  • Page 558 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value 0xE900_0130 Channel Status for DMA Channel 6 0xE900_0138 Channel Status for DMA Channel 7 Channel Program Counter Registers. For more information refer to “Page 3-26 of PL330 TRM” CPC0...
  • Page 559 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Register Address Description Reset Value CC_5 0xE900_04A8 Channel Control for DMA Channel 5 CC_6 0xE900_04C8 Channel Control for DMA Channel 6 CC_7 0xE900_04E8 Channel Control for DMA Channel 7 Loop Counter 0 Registers. For more information refer to “Page 3-35 of PL330 TRM”...
  • Page 560 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value Debug Command Register. For more information DBGCMD 0xE900_0D04 refer to “Page 3-37 of PL330 TRM” Debug Instruction-0 Register. For more information DBGINST0 0xE900_0D08 refer to “Page 3-38 of PL330 TRM”...
  • Page 561 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Table 6.1-4 DMA_peri1 Register Summary Register Address Description Reset Value DMA Status Register. For more information refer to 0xE920_0000 “Page 3-11 of PL330 TRM” DMA Program Counter Register. For more 0xE920_0004 information refer to “Page 3-13 of PL330 TRM”...
  • Page 562 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value 0xE920_0130 Channel Status for DMA Channel 6 0xE920_0138 Channel Status for DMA Channel 7 Channel Program Counter Registers. For more information refer to “Page 3-26 of PL330 TRM” CPC0...
  • Page 563 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Register Address Description Reset Value CC_5 0xE920_04A8 Channel Control for DMA Channel 5 CC_6 0xE920_04C8 Channel Control for DMA Channel 6 CC_7 0xE920_04E8 Channel Control for DMA Channel 7 Loop Counter 0 Registers. For more information refer to “Page 3-35 of PL330 TRM”...
  • Page 564 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value Debug Status Register. For more information refer DBGSTATUS 0xE920_0D00 to “Page 3-37 of PL330 TRM” Debug Command Register. For more information DBGCMD 0xE920_0D04 refer to “Page 3-37 of PL330 TRM”...
  • Page 565 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER 3.2 DETAILED DESCRIPTION 3.2.1 Channel Control Register for DMA_mem (CC, R) • CC_0, R, Address = 0xE810_0408 • CC_1, R, Address = 0xE810_0428 • CC_2, R, Address = 0xE810_0448 • CC_3, R, Address = 0xE810_0468 •...
  • Page 566 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.2.2 Channel Control Register for DMA_PERI(0,1) (CC, R) • CC_0, R, Address = 0xE900_0408, 0xE920_0408 • CC_1, R, Address = 0xE900_0428, 0xE920_0428 • CC_2, R, Address = 0xE900_0448, 0xE920_0448 • CC_3, R, Address = 0xE900_0468, 0xE920_0468 •...
  • Page 567 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER 3.2.3 Configuration Register0 for DMA_PERI(0,1) (CR0, R) • CR0 for DMA_PERI0, R, Address = 0xE900_0E00 • CR0 for DMA_PERI1, R, Address = 0xE920_0E00 Description Reset Value Number of interrupt outputs that the DMAC provides...
  • Page 568 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.2.4 Configuration Register1 for DMA_PERI(0,1) (CR1, R) • CR1 for DMA_PERI0, R, Address = 0xE900_0E04 • CR1 for DMA_PERI1, R, Address = 0xE920_0E04 Description Reset Value Read value is always 7. It means DMA_PERI(0,1) has 8 i-...
  • Page 569 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER 3.2.7 Configuration Register4 for DMA_PERI(0,1) (CR4, R) • CR4 for DMA_PERI0, R, Address = 0xE900_0E10 • CR4 for DMA_PERI1, R, Address = 0xE920_0E10 Description Reset Value Provides the security state of the peripheral request interfaces:...
  • Page 570 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.2.9 Configuration Register0 for DMA_mem (CR0, R, Address=0xE810_0E00) Description Reset Value Number of interrupt outputs that the DMAC provides num_events [21:17] 0x1F b11111 = 32 interrupt outputs, irq[31:0] Number of peripheral request interfaces that the DMAC...
  • Page 571 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER 3.2.11 Configuration Register2 for DMA_MEM (CR2, R, Address=0xE810_0E08) Description Reset Value Provides the value of boot_addr[31:0] when the DMAC exited from reset boot_addr [31:0] 32’b0 3.2.12 Configuration Register3 for DMA_MEM (CR3, R, Address=0xE810_0E0C) Description...
  • Page 572 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.2.14 Configuration Register DN for DMA_MEM (CRdn, R, Address=0xE810_0E14) CRDn Description Reset Value The number of lines that the data buffer contains data_buffer_dep [29:20] 0x1F b000011111 = 32 lines The depth of the read queue...
  • Page 573 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER 4 INSTRUCTION Table 6.1-5 Instruction Syntax Summary Thread usage: Mnemonic Instruction Description M = DMA manager C = DMA channel PL330 See DMAADDH on page 4-5 of “ DMAADDH Add Halfword TRM” PL330 DMAEND See DMAEND on page 4-5 of “...
  • Page 574 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.1 KEY INSTRUCTION To run channel thread, you must write assembly code. Compared to PC assembly, it is very simple. The description of key instruction is listed below. For full instruction set refer to “Chapter 4 of PL330 TRM”.
  • Page 575 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER DMALP, DMALPEND “DMALP lc0, 4 bla~bla~ DMALPEND lc0” loops “bla~bla~” 4 times. There are 2 loop counters, lc0 and lc1. You can use nested loop by 2 loop counters. DMAWFP This is used for peripheral DMA. Wait for Peripheral instructs the DMAC to halt execution of the thread until the specified peripheral signals a DMA request for that DMA channel.
  • Page 576 DMA CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2 USAGE MODEL PL330 needs its own binary. 1. Load DMA binary into memory. 2. Use DMA debug SFRs to start DMA controller, PL330. A. Using debug SFRs √ DBGCMD, DBGINST0, and DBGINST1 (all write-only) √...
  • Page 577 S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER Interrupts The DMAC provides the irq signals to use as active-high level-sensitive interrupts to external CPUs. If you program the Interrupt Enable Register to generate an interrupt, after the DMAC executes it sets the DMASEV corresponding irq HIGH.
  • Page 578 PULSE WIDTH MODULATION TIMER 1 OVERVIEW The S5PC100 has five 32-bit timers. These timers generate internal interrupts to the ARM subsystem. In addition, Timers 0, 1, and 2 include a Pulse Width Modulation (PWM) function which drives an external I/O signal. The PWM for timer 0 has an optional dead-zone generator capability to support a large current device.
  • Page 579 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) The Figure 7.1-1 shows a simple example of a PWM cycle. TOUTn Figure 7.1-1 Simple Example of PWM Cycle Initialize TCNTBn with 159(50+109) and TCMPBn with 109. Start Timer: Set the start bit and manual update bit to off.
  • Page 580 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER TCMPB0 TCNTB0 PCLK XpwmTOUT0 PWM_TCLK DeadZone Control Generator Logic0 Deadzone 8BIT PRESCALER TCMPB1 TCNTB1 1/16 XpwmTOUT1 Control Logic1 PWM_TCLK PWM_TCLK Deadzone TCMPB2 TCNTB2 PWM_TCLK XpwmTOUT2 Control Logic2 TCMPB3 TCNTB3 PWM_TCLK No pin...
  • Page 581 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 2 FEATURES The Features supported by the PWM include: • Five 32-bit Timers. • Two 8-bit Clock Prescalers providing first level of division for the PCLK, Five Clock Dividers and Multiplexers providing second level of division for the Prescaler clock and one External Clock •...
  • Page 582: Pwm Operation

    S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER 3 PWM OPERATION 3.1 PRESCALER & DIVIDER An 8-bit prescaler and 3-bit divider makes the following output frequencies: Table 7.1-1 Minimum and Maximum Resolution based on Prescaler and Clock Divider Values Minimum Resolution...
  • Page 583 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 3.2 BASIC TIMER OPERATION auto-reload start bit=1 timer is started TCNTn=TCMPn TCNTn=TCMPn timer is stopped. TCMPn TCNTn auto-reload=0 TCNTBn=3 TCNTBn=2 interrupt request interrupt request TCMPBn=1 TCMPBn=0 manual update=1 manual update=0 auto-reload=1 auto-reload=1...
  • Page 584 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER 3.3 AUTO-RELOAD AND DOUBLE BUFFERING The Timers have a double buffering feature, which changes the reload value for the next timer operation without stopping the current timer operation. Even though the new timer value is set, a current timer operation completes successfully.
  • Page 585 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 3.4 TIMER OPERATION EXAMPLE The result of the following procedure is shown in Figure 7.1-5. TOUTn Figure 7.1-5 Example of a Timer Operation 1. Enable the auto-reload feature. Set the TCNTBn as 159(50+109) and TCMPBn as 109. Set the manual update bit on and set the manual update bit off.
  • Page 586 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER 3.5 INITIALIZE TIMER (SETTING MANUAL-UP DATA AND INVERTER) Because an auto-reload operation of the timer occurs when the down counter reaches to 0, a starting value of the TCNTn has to be defined by the user at first. In this case, the starting value must be loaded by manual update bit.
  • Page 587 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 3.7 OUTPUT LEVEL CONTROL Inverter off inverter on Initial State Period 1 Period 2 Timer stop Figure 7.1-7 Inverter On/Off The steps to maintain TOUT as high or low (Assume that inverter is off).
  • Page 588 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER TOUT0 nTOUT0 DEADZONE INTERVAL TOUT0_DZ nTOUT0_DZ Figure 7.1-8 The Waveform when a Dead Zone Feature is Enabled. 7.1-11...
  • Page 589 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 4 I/O DESCRIPTION Funtion Signal Descrioption Type TOUT0 Output PWMTIMER TOUT[0] XpwmTOUT[0] muxed TOUT1 Output PWMTIMER TOUT[1] XpwmTOUT[1] muxed TOUT2 Output PWMTIMER TOUT[2] XpwmTOUT[2] muxed PWM_TCLK Input PWMTIMER External Clock XpwmTOUT[0] muxed NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals.
  • Page 590 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER 5 REGISTER DESCRIPTION Register Address Description Reset Value TCFG0 0xEA00_0000 Timer Configuration Register 0 that configures the 0x0000_0101 two 8-bit Prescaler and DeadZone Length TCFG1 0xEA00_0004 Timer Configuration Register 1 that controls 5...
  • Page 591 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 5.1 TIMER CONFIGURATION REGISTER (TCFG0, R/W, ADDRESS = 0XEA00_0000) Timer Input Clock Frequency = PCLK / ( {prescaler value + 1} ) / {divider value} {prescaler value} = 1~255 {divider value} = 1, 2, 4, 8, 16, TCLK...
  • Page 592 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER 5.2 TIMER CONFIGURATION REGISTER (TCFG1, R/W, ADDRESS = 0XEA00_0004) TCFG1 Description Reset Value Reserved [31:24] Reserved Bits 0x00 Selects Mux input for PWM Timer 4 0000 = 1/1 0001 = 1/2 Divider MUX4...
  • Page 593 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 5.3 TIMER CONTROL REGISTER (CON, R/W, ADDRESS = 0XEA00_0008) TCON Description Reset Value Reserved [31:23] Reserved Bits 0x000 0 = One-Shot Timer 4 Auto Reload on/off [22] 1 = Interval Mode(Auto-Reload) 0 = No Operation...
  • Page 594 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER If Manual update bit is 1’b1 and Start/Stop bit is 1’b1, timer counter is not update by new value. Timer counter value is last value. 5.4 TIMER0 COUNTER REGISTER (TCNTB0, R/W, ADDRESS = 0XEA00_000C)
  • Page 595 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 5.9 TIMER1 OBSERVATION REGISTER (TCNTO1, R, ADDRESS = 0XEA00_0020) TCNTO1 Description Reset Value Timer 1 Count Observation [31:0] Timer 1 Count Observation Register 0x0000_0000 NOTE: Counter observation time is dependent on PWM timer clock and PCLK.
  • Page 596 S5PC100 USER’S MANUAL (REV1.0) PULSE WIDTH MODULATION TIMER 5.15 TIMER4 COUNTER REGISTER (TCNTB4, R/W, ADDRESS = 0XEA00_003C) TCNTB4 Description Reset Value Timer 4 Count Buffer [31:0] Timer 4 Count Buffer Register 0x0000_0000 5.16 TIMER4 OBSERVATION REGISTER (TCNTO4, R, ADDRESS = 0XEA00_0040)
  • Page 597 PULSE WIDTH MODULATION TIMER S5PC100 USER’S MANUAL (REV1.0) 5.17 INTERRUPT CONTROL AND STATUS REGISTER (TINT_CSTAT, R/W, ADDRESS = 0XEA00_0044) TINT_CSTAT Description Reset Value Reserved [31:10] Reserved Bits 0x00000 Timer 4 Interrupt Status Bit. Clears by writing ‘1’ on Timer 4 Interrupt Status this bit.
  • Page 598 S5PC100 USER’S MANUAL (REV1.0) SYSTEM TIMER SYSTEM TIMER 1 OVERVIEW System timer provides two distinctive features. First one is accurate timer which provides 1ms time tick at any power mode except sleep mode. Second one is changeable interrupt interval without stopping reference tick timer.
  • Page 599 SYSTEM TIMER S5PC100 USER’S MANUAL (REV1.0) 2 FEATURES • Clock sources of ST: main OSC (XXTI), RTC OSC (XrtcXTI), USB OSC (XusbXTI), and PCLKD1 • Counter bit: 32-bit • Changeable interrupt-interval without stopping reference tick timer • Used at any power mode except sleep mode.
  • Page 600 S5PC100 USER’S MANUAL (REV1.0) SYSTEM TIMER 4 INTERNAL FUNCTION TICK Generation Interrupt Generation region region User Change User Change TICNTB, TFCNTB Interrupt Interval Counter Value (Tick Count Buffer Register ) Counter (ICNTB ) Value (Timer Stop ) (Without Timer Stop )
  • Page 601 SYSTEM TIMER S5PC100 USER’S MANUAL (REV1.0) 5 DETAILED OPEARATION Figure 7.2-3 Timer Operation with Always on of Auto-reload Generally tick interval is fixed after initial setting. And interrupt interval can be changed at run-time. Figure 7.2-3 shows detailed operation of interrupt counter and interrupt counter observation SFR with auto-reload. Each rectangular shows one tick time.
  • Page 602 S5PC100 USER’S MANUAL (REV1.0) SYSTEM TIMER When Interrupt Manual Update (TCON[4]) is asserted off, after timer is expired, INTCNT (interrupt counter) is set as 0. And interrupt is occurred at every TICK. 6 USAGE MODEL Follow the restrictions given below: •...
  • Page 603 SYSTEM TIMER S5PC100 USER’S MANUAL (REV1.0) 6.3 START TIMER 1. Set TCFG SFR to make appropriate TCLK. A. Select clock source. B. Set pre-scaler and divider value. 2. Set tick counter by writing to TCNTB SFR. 3. Wait until TCNTB write interrupt occurs, and write 1 to INT_CSTAT[2] to clear interrupt status bit.
  • Page 604 S5PC100 USER’S MANUAL (REV1.0) SYSTEM TIMER 7 REGISTER DESCRIPTION 7.1 REGISTER SUMMARY Register Address Description Reset Value TCFG Configures 8-bit-Prescaler and Clock MUX EA10_0000 0x0000_0000 TCON Timer Control Register EA10_0004 0x0000_0000 TCNTB EA10_0008 Tick Count Buffer Register 0x0000_0000 TCNTO Tick Count Observation Register...
  • Page 605 SYSTEM TIMER S5PC100 USER’S MANUAL (REV1.0) 7.2 DETAILED DESCRIPTION 7.2.1 TIMER CONFIGURATION REGISTER (TCFG, R/W, Address = EA10_0000) Timer Input Clock Frequency = TCLKB / ( {prescaler value + 1} ) / {divider value} {prescaler value} = 1~63 / {divider value} = 1, 2, 4, 8, 16...
  • Page 606 S5PC100 USER’S MANUAL (REV1.0) SYSTEM TIMER 7.2.2 TIMER CONTROL REGISTER (TCON, R/W, Address = EA10_0004) TCON Description Reset Value Interrupt Auto Reload On/ 0 = No operation 1 = Interval mode (auto-reload) 0 = No operation Interrupt Manual Update 1 = Update ICNTB and One-shot mode...
  • Page 607 SYSTEM TIMER S5PC100 USER’S MANUAL (REV1.0) 7.2.4 TICK OBSERVATION REGISTER (TCNTO, R, Address = EA10_000C) TCNTO Description Reset Value Tick Count Observation [31:0] Tick Count Observation Register 7.2.5 INTERRUPT COUNTER REGISTER (ICNTB, R/W, Address = EA10_0010) Real Interrupt Counter Value = ICNTB+1.
  • Page 608: Watchdog Timer

    1 OVERVIEW The S5PC100 Watchdog Timer (WDT) is used to resume the controller operation if it is disturbed by malfunctions such as noise and system errors. It is used as a normal 16-bit interval timer to request interrupt service. The WDT generates the reset signal.
  • Page 609 To start WDT, set WTCON[0] and WTCON[5] as 1. 3.4 CONSIDERATION OF DEBUGGING ENVIRONMENT If the S5PC100 is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer determines whether it is currently in the debug mode from the CPU core signal (DBGACK signal).
  • Page 610 The WTCON register allows you to enable/ disable the watchdog timer, select the clock signal from 4 different sources, enable/ disable interrupts, and enable/ disable the watchdog timer output. The Watchdog timer is used to resume the S5PC100 restart on mal-function after its power on; if controller restart is not desired, the Watchdog timer should be disabled.
  • Page 611 WATCHDOG TIMER S5PC100 USER’S MANUAL (REV1.0) 4.2 WATCHDOG TIMER DATA REGISTER (WTDAT, R/W, ADDRESS = 0XEA20_0004) The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) drives the first time-out.
  • Page 612 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK REAL TIME CLOCK (RTC) 1 OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The data include the time by Second, Minute, Hour, Date, Day, Month, and Year. The RTC unit works with an external 32.768 kHz crystal and performs the alarm function.
  • Page 613 For example, it cannot discriminate between 1900 and 2000. To solve this problem, the RTC block in S5PC100 has hard-wired logic to support the leap year in 2000. Note 1900 is not leap year while 2000 is leap year.
  • Page 614 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK 6 BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery, which supplies the power through the RTCVDD pin into the RTC block, even if the system power is off. If the system is off, the interfaces of the CPU and RTC logic should be blocked, and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation.
  • Page 615 REAL TIME CLOCK S5PC100 USER’S MANUAL (REV1.0) 8 TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches ‘0’ if the tick time interrupt occurs. Then the period of interrupt is as...
  • Page 616 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK 9 32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 7.4-2 shows a circuit of the RTC unit oscillation at 32.768kHz. 15~ 22pF XrtcXTI 32768 Hz XrtcXTO Figure 7.4-2 Main Oscillator Circuit Example Note. The external components commonly used for the above circuit are a resonator, two capacitors(15~22 pF) and a resistor(>5MΩ) between XrtcXTI and XrtcXTO.
  • Page 617 REAL TIME CLOCK S5PC100 USER’S MANUAL (REV1.0) 13 REGISTER DESCRIPTION Register Address Description Reset Value INTP 0xEA30_0030 Interrupt Pending Register 0x00000000 RTCCON 0xEA30_0040 RTC Control Register 0x00000000 TICCNT 0xEA30_0044 Tick Time Count Register 0x00000000 RTCALM 0xEA30_0050 RTC Alarm Control Register...
  • Page 618 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK 13.1 INTERRUPT PENDING REGISTER (INTP, R/W, ADDRESS = 0XEA30_0030) You can clear specific bits of INTP register by writing 1’s to the bits that you want to clear regardless of RTCEN value. INTP...
  • Page 619 REAL TIME CLOCK S5PC100 USER’S MANUAL (REV1.0) 13.2 REAL TIME CLOCK CONTROL REGISTER (RTCCON, R/W, ADDRESS = 0XEA30_0040) The RTCCON register consists of 9 bits such as the RTCEN, which controls the read/ write enable of the BCD SEL, CNTSEL, CLKRST, TICCKSEL and TICEN for testing.
  • Page 620 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK 13.3 TICK TIME COUNT REGISTER (TICNT, R/W, ADDRESS = 0XEA30_0044) TICNT Description Reset Value 32-bit tick time count value TICK TIME [31:0] 32’b0 COUNT This value must not be 0. 13.4 RTC ALARM CONTROL REGISTER (RTCALM, R/W, ADDRESS = 0XEA30_0050) The RTCALM register determines the alarm enable and the alarm time.
  • Page 621 REAL TIME CLOCK S5PC100 USER’S MANUAL (REV1.0) 13.5 ALARM SECOND DATA REGISTER (ALMSEC, R/W, ADDRESS = 0XEA30_0054) ALMSEC Description Reset Value Reserved [31:7] Reserved BCD value for alarm second. [6:4] 0 ~ 5 SECDATA [3:0] 0 ~ 9 0000 13.6 ALARM MIN DATA REGISTER (ALMMIN, R/W, ADDRESS = 0XEA30_0058)
  • Page 622 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK 13.9 ALARM MONTH DATA REGISTER (ALMMON, R/W, ADDRESS = 0XEA30_0064) ALMMON Description Reset Value Reserved [31:5] Reserved BCD value for alarm month. 0 ~ 1 MONDATA [3:0] 0 ~ 9 0000 13.10 ALARM YEAR DATA REGISTER (ALMYEAR, R/W, ADDRESS = 0XEA30_0068)
  • Page 623 REAL TIME CLOCK S5PC100 USER’S MANUAL (REV1.0) 13.13 BCD HOUR REGISTER (BCDHOUR, R/W, ADDRESS = 0XEA30_0078) BCDHOUR Description Reset Value Reserved [31:6] Reserved BCD value for hour. [5:4] 0 ~ 2 HOURDATA [3:0] 0 ~ 9 13.14 BCD DATE REGISTER (BCDDATE, R/W, ADDRESS = 0XEA30_007C)
  • Page 624 S5PC100 USER’S MANUAL (REV1.0) REAL TIME CLOCK 13.17 BCD YEAR REGISTER (BCDYEAR, R/W, ADDRESS = 0XEA30_0088) BCDYEAR Description Reset Value Reserved [31:8] Reserved BCD value for year. [7:4] 0 ~ 9 YEARDATA [3:0] 0 ~ 9 13.18 TICK COUNTER REGISTER (CURTICCNT, R, ADDRESS = 0XEA30_0090)
  • Page 625 AND TRANSMITTER 1 OVERVIEW The S5PC100 Universal Asynchronous Receiver and Transmitter (UART) provide four independent asynchronous serial Input/ Output (I/O) (SIO) ports. Both the ports operate in interrupt-based or DMA-based mode. In other words, UART generates an interrupt or a DMA request to transfer data between CPU and the UART. The UART ch0, ch2 supports bit rates up to 115.2K bps and UART ch1 and ch3 supports bit rates up to 3M bps.
  • Page 626 UART S5PC100 USER’S MANUAL (REV1.0) Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Buad-rate Clock Source Unit Generator Receiver Receive Shifter RXDn Receive Holding Register (Non-FIFO mode only)
  • Page 627 3.3 AUTO FLOW CONTROL(AFC) The S5PC100's UART0 and UART1 support auto flow control with nRTS and nCTS signals. UART2 supports auto flow control if TxD3 and RxD3 are set as nRTS2 and nCTS2 by GPA1CON(GPIO SFR). In case, it can be connected to external UARTs.
  • Page 628 AFC does not support the RS-232C interface. 3.6 INTERRUPT/DMA REQUEST GENERATION Each UART of the S5PC100 has seven status (Tx/Rx/Error) signals, namely: Overrun error, Parity error, Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty. These conditions are indicated by the corresponding UART status register (UTRSTATn/UERSTATn).
  • Page 629 It is recommended to fill the Tx buffer first and then enable the Tx interrupt. The interrupt controllers of S5PC100 are level-triggered type. You must set the interrupt type as ‘Level’ if you program the UART control registers.
  • Page 630 UART S5PC100 USER’S MANUAL (REV1.0) Time Sequence Flow Error Interrupt Note If no character is read out A, B, C, D, and E is received After A is read out Frame error (in B) interrupt occurs. The 'B' has to be read out.
  • Page 631 3.7.1 Infra-Red (IR) Mode The S5PC100 UART block supports infra-red (IR) transmission and reception. It is selected by setting the Infra- red-mode bit in the UART line control register (ULCONn). Figure 8.1- illustrates how to implement the IR mode. In IR transmit mode, the transmit pulse comes out at a rate of 3/16, the normal serial transmit rate (If the transmit data bit is 0);...
  • Page 632 UART S5PC100 USER’S MANUAL (REV1.0) IR Transmit Frame Data Bits Start Stop Pulse Width = 3/16 Bit Frame Time Figure 8.1-6 Infra-Red Transmit Mode Frame Timing Diagram IR Receive Frame Data Bits Start Stop Figure 8.1-7 Infra-Red Receive Mode Frame Timing Diagram...
  • Page 633 S5PC100 USER’S MANUAL (REV1.0) UART UART INPUT CLOCK DIAGRAM DESCRIPTION Clock Controller UART APLL Out UCLK_Generator SCLK_UART MPLL Out BCLK UCLK EPLL Out PCLK UBDIV UDIVSLOT XuCLK Clock_Selection[11:10] Figure 8.1-8 Input Clock Diagram for UART S5PC100X provides UART with a variety of clock. As described in the Figure 8.1-, UART is able to select clock from PCLK, XuCLK which come from PAD or SCLK_UART which is from clock controller.
  • Page 634 UART S5PC100 USER’S MANUAL (REV1.0) 5 I/O DESCRIPTION Function Signal Descrioption Type Input Receive Data for UART0 XuRXD[0] muxed UART0_RXD Output Transmit Data for UART0 XuTXD[0] muxed UART0_TXD CTSn Input Clear to Send(active low) for UART0 XuCTSn[0] muxed UART0_ RTSn...
  • Page 635 S5PC100 USER’S MANUAL (REV1.0) UART 6 REGISTER DESCRIPTION Register Address Description Reset Value ULCON0 0xEC00_0000 UART Channel 0 Line Control Register 0x00 UCON0 0xEC00_0004 UART Channel 0 Control Register 0x00 UFCON0 0xEC00_0008 UART Channel 0 FIFO Control Register UMCON0 0xEC00_000C...
  • Page 636 UART S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value ULCON2 0xEC00_0800 UART Channel 2 Line Control Register 0x00 UCON2 0xEC00_0804 UART Channel 2 Control Register 0x00 UFCON2 0xEC00_0808 UART Channel 2 FIFO Control Register UMCON2 0xEC00_080C UART Channel 2 Modem Control Register...
  • Page 637 S5PC100 USER’S MANUAL (REV1.0) UART 6.1 UART LINE CONTROL REGISTER • ULCON0, R/W, Address = 0xEC00_0000 • ULCON1, R/W, Address = 0xEC00_0400 • ULCON2, R/W, Address = 0xEC00_0800 • ULCON3, R/W, Address = 0xEC00_0C00 There are four UART line control registers namely ULCON0, ULCON1, ULCON2, and ULCON3 in the UART block.
  • Page 638 UART S5PC100 USER’S MANUAL (REV1.0) 6.2 UART CONTROL REGISTER • UCON0, R/W, Address = 0xEC00_0004 • UCON1, R/W, Address = 0xEC00_0404 • UCON2, R/W, Address = 0xEC00_0804 • UCON3, R/W, Address = 0xEC00_0C04 There are four UART control registers namely UCON0, UCON1, UCON2 and UCON3 in the UART block.
  • Page 639 DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16. Refer to UART Buad Rate Configure Registers RX interrupt type must be set to pulse for every transfer in S5PC100. If the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt is generated (receive time out), and you must check the FIFO status and read out the rest.
  • Page 640 UART S5PC100 USER’S MANUAL (REV1.0) UART FIFO Control Register • UFCON0, R/W, Address = 0xEC00_0008 • UFCON1, R/W, Address = 0xEC00_0408 • UFCON2, R/W, Address = 0xEC00_0808 • UFCON3, R/W, Address = 0xEC00_0C08 There are four UART FIFO control registers namely UFCON0, UFCON1, UFCON2 and UFCON3 in the UART block.
  • Page 641 1 = 'L' level (Activate nRTS) NOTE: UART 2 supports AFC function, if nRxD3 and nTxD3 are set as nRTS2 and nCTS2 by GPA1CON. UART 3 does not support AFC function, because the S5PC100 has no nRTS3 and nCTS3. 8.1-17...
  • Page 642 UART S5PC100 USER’S MANUAL (REV1.0) 6.4 UART TX/RX STATUS REGISTER • UTRSTAT0, R, Address = 0xEC00_0010 • UTRSTAT1, R, Address = 0xEC00_0410 • UTRSTAT2, R, Address = 0xEC00_0810 • UTRSTAT3, R, Address = 0xEC00_0C10 There are four UART Tx/Rx status registers namely UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in the UART block.
  • Page 643 S5PC100 USER’S MANUAL (REV1.0) UART 6.5 UART ERROR STATUS REGISTER • UERSTAT0, R, Address = 0xEC00_0014 • UERSTAT1, R, Address = 0xEC00_0414 • UERSTAT2, R, Address = 0xEC00_0814 • UERSTAT3, R, Address = 0xEC00_0C14 There are four UART Rx error status registers namely UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3 in the UART block.
  • Page 644 UART S5PC100 USER’S MANUAL (REV1.0) 6.6 UART FIFO STATUS REGISTER • UFSTAT0, R, Address = 0xEC00_0018 • UFSTAT1, R, Address = 0xEC00_0418 • UFSTAT2, R, Address = 0xEC00_0818 • UFSTAT3, R, Address = 0xEC00_0C18 There are four UART FIFO status registers namely UFSTAT0, UFSTAT1, UFSTAT2 and UFSTAT3 in the UART...
  • Page 645 Reserved [7:5] reserved Delta CTS This bit indicates that the nCTS input to the S5PC100 has changed its state since the last time it was read by CPU. (Refer Figure 8.1-) 0 = Has not changed 1 = Has changed...
  • Page 646 UART S5PC100 USER’S MANUAL (REV1.0) 6.8 UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) • UTXH0, W, Address = 0xEC00_0020 • UTXH1, W, Address = 0xEC00_0420 • UTXH2, W, Address = 0xEC00_0820 • UTXH3, W, Address = 0xEC00_0C20 There are four UART transmit buffer registers namely UTXH0, UTXH1, UTXH2 and UTXH3 in the UART block.
  • Page 647 S5PC100 USER’S MANUAL (REV1.0) UART 6.10 UART CHANNEL BAUD RATE DIVISIOR REGISTER • UBRDIV0, R/W, Address = 0xEC00_0028 • UBRDIV1, R/W, Address = 0xEC00_0428 • UBRDIV2, R/W, Address = 0xEC00_0828 • UBRDIV3, R/W, Address = 0xEC00_0C28 UBRDIV n Description Reset Value...
  • Page 648 UART S5PC100 USER’S MANUAL (REV1.0) NOTE: 1) UART Baud Rate Configuration There are four UART baud rate divisor registers namely UBRDIV0, UBRDIV1, UBRDIV2 and UBRDIV3 in the UART block. The value stored in the baud rate divisor register (UBRDIVn) and dividing slot register(UDIVSLOTn), are used to...
  • Page 649 S5PC100 USER’S MANUAL (REV1.0) UART 2) Baud Rate Error Tolerance UART Frame error should be less than 1.87%(3/160) tUPCLK = (UBRDIVn + 1) x 16 x 1Frame / (PCLK ,UART_CLK or SCLK_UART) tUPCLK: Real UART Clock tEXTUARTCLK = 1Frame / baud-rate tEXTUARTCLK: Ideal UART Clock UART error = (tUPCLK −...
  • Page 650 UART S5PC100 USER’S MANUAL (REV1.0) 6.13 UART INTERRUPT SOURCE PENDING REGISTER • UINTSP0, R/W, Address = 0xEC00_0034 • UINTSP1, R/W, Address = 0xEC00_0434 • UINTSP2, R/W, Address = 0xEC00_0834 • UINTSP3, R/W, Address = 0xEC00_0C34 Interrupt Source Pending Register contains the information of the interrupt that are generated regardless of the...
  • Page 651 S5PC100 USER’S MANUAL (REV1.0) UART Figure 8.1-10 UINTSP, UINTP and UINTM block diagram 8.1-27...
  • Page 652 UART S5PC100 USER’S MANUAL (REV1.0) NOTES 8.1-28...
  • Page 653 C -bus. The SDA and SCL lines are bi-directional. In the multi-master I C-bus mode, multiple microprocessors receive or transmit serial data to or from slave devices. The master S5PC100 initiates and terminates a data transfer over the I C-bus. The I C-bus in the S5PC100 uses Standard bus arbitration procedure.
  • Page 654 C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) Address Register Comparator I2C-Bus Control Logic I2CCON I2CSTAT 4-bit Prescaler Shift Register PCLK Shift Register (I2CDS) Data Bus Figure 8.2-1 I C-Bus Block Diagram 1.1 I C-BUS INTERFACE The S5PC100 I C-bus interface has four operation modes: •...
  • Page 655 S5PC100 USER’S MANUAL (REV1.0) C-BUS INTERFACE Start Stop Condition Condition Figure 8.2-2 Start and Stop Condition 1.3 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. There is no limit to transmit bytes per transfer.
  • Page 656 C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) Acknowledgement Acknowledgement Signal from Receiver Signal from Receiver Byte Complete, Interrupt Clock Line Held Low by within Receiver receiver and/or transmitter Figure 8.2-4 Data Transfer on the I C-Bus 1.4 ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse occurs at the ninth clock of the SCL line.
  • Page 657 C-bus interface waits until I2CDS register is read. Before the new data is read out, the SCL line is held low and then released after it is read. The S5PC100 holds the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it reads the data from the I2CDS register.
  • Page 658 C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) START Master Tx mode has been configured. Write slave address to I2CDS. Write 0xF0 (M/T Start) to I2CSTAT. The data of the I2CDS is transmitted. After ACK period interrupt is pending. Stop? Write new data Write 0xD0 (M/T Stop) transmitted to I2CDS.
  • Page 659 S5PC100 USER’S MANUAL (REV1.0) C-BUS INTERFACE START Master Rx mode has been configured. Write slave address to I2CDS. Write 0xB0 (M/R Start) to I2CSTAT. The data of the I2CDS (slave address) is transmitted. After ACK period interrupt is pending. Stop?
  • Page 660 C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) START Slave Tx mode has been configured. I2C detects start signal. and, I2CDS receives data. I2C compares I2CADD and I2CDS (the received slave address). Matched? The I2C address match interrupt is generated. Write data to I2CDS.
  • Page 661 S5PC100 USER’S MANUAL (REV1.0) C-BUS INTERFACE START Slave Rx mode has been configured. I2C detects start signal. and, I2CDS receives data. I2C compares I2CADD and I2CDS (the received slave address). Matched? The I2C address match interrupt is generated. Read data from I2CDS.
  • Page 662 C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) I/O DESCRIPTION Function Signal Descrioption Type I2C0_SCL Input/Output C-Bus Interface0 Serial Clock Line Xi2c0SCL muxed I2C0_SDA Input/Output C-Bus Interface0 Serial Data Line Xi2c0SDA muxed I2C1_SCL Input/Output C-BUS Interface1 Serial Clock Line Xi2c1SCL muxed I2C1_SDA...
  • Page 663 S5PC100 USER’S MANUAL (REV1.0) C-BUS INTERFACE 3.1 MULTI-MASTER I C-BUS CONTROL REGISTER • I2CCON0, R/W, Address = 0xEC10_0000 • I2CCON1, R/W, Address = 0xEC20_0000 I2CCON Description Reset Value Acknowledge generation C-bus acknowledge enable bit. 0 = Disables 1 = Enables In Tx mode, the I2CSDA is free in the ACK time.
  • Page 664 C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0) 3.2 MULTI-MASTER I C-BUS CONTROL/STATUS REGISTER • I2CSTAT0, R/W, Address = 0xEC10_0004 • I2CSTAT1, R/W, Address = 0xEC20_0004 I2CSTAT Description Reset Value Mode selection [7:6] C-bus master/ slave Tx/Rx mode select bits. 00 = Slave receive mode...
  • Page 665 S5PC100 USER’S MANUAL (REV1.0) C-BUS INTERFACE 3.3 MULTI-MASTER I C-BUS ADDRESS REGISTER • I2CADD0, R/W, Address = 0xEC10_0008 • I2CADD1, R/W, Address = 0xEC20_0008 I2CADD Description Reset Value Slave address [7:0] 7-bit slave address, latched from the I C-bus. Undefined If serial output enable = 0 in the I2CSTAT, I2CADD is write- enabled.
  • Page 666: Spi Controller

    SPI CONTROLLER 1 OVERVIEW The Serial Peripheral Interface (SPI) in S5PC100 transfers serial data using various peripherals. SPI includes two 8, 16, 32-bit shift registers for the purpose of transmission and receiving. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface.
  • Page 667 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.1 OPERATION The SPI transfers 1-bit serial data between S5PC100x and external device. The SPI in S5PC100x supports the CPU or DMA to transmit or receive FIFOs separately and to transfer data in both directions simultaneously. SPI has 2 channels, TX channel and RX channel.
  • Page 668 S5PC100 USER’S MANUAL (REV1.0) SPI CONTROLLER 2.1.4 Packet Number Control SPI controls the number of packets to be received in master mode. Set SFR (Packet_Count_reg) to receive any number of packets. SPI stops generating SPICLK if the number of packets is the same as what you had set. It is mandatory to follow software or hardware reset before this function is reloaded.
  • Page 669 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 2.1.7 SPI Transfer Format The S5PC100 supports 4 different formats for data transfer. Figure 8.3-2 describes four waveforms for SPICLK. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO *MSB *MSB : MSB of previous frame...
  • Page 670 S5PC100 USER’S MANUAL (REV1.0) SPI CONTROLLER 3 I/O DESCRIPTION The following table lists the external signals between the SPI and external device. The unused SPI ports are used as General Purpose I/O ports. Refer Chapter "General Purpose I/O" for detail information.
  • Page 671 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 REGISTER DESCRIPTION Register Address Description Reset Value CH_CFG(Ch0) 0xEC30_0000 SPI Configuration Register 0x40 CH_CFG(Ch1) 0xEC40_0000 SPI Configuration Register 0x40 CH_CFG(Ch2) 0xEC50_0000 SPI Configuration register 0x40 CLK_CFG(Ch0) 0xEC30_0004 Clock Configuration Register CLK_CFG(Ch1) 0xEC40_0004 Clock Configuration Register...
  • Page 672 S5PC100 USER’S MANUAL (REV1.0) SPI CONTROLLER 4.1 PROGRAMMING GUIDE Special Function Register should be set as the following sequence. (nCS manual mode) 1. Set Transfer Type (CPOL & CPHA set). 2. Set Clock configuration register. 3. Set SPI MODE configuration register.
  • Page 673 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2 DETAILED DESCRIPTION 4.2.1 SPI Configuration Register • CH_CFG0, R/W, Address = 0xEC30_0000 • CH_CFG1, R/W, Address = 0xEC40_0000 • CH_CFG2, R/W, Address = 0xEC50_0000 CH_CFGn Description Reset value HIGH_SPEED_EN Slave TX output time control bit.
  • Page 674 S5PC100 USER’S MANUAL (REV1.0) SPI CONTROLLER 4.2.3 SPI FIFO Control Register • MODE_CFG0, R/W, Address = 0xEC30_0008 • MODE_CFG1, R/W, Address = 0xEC40_0008 • MODE_CFG2, R/W, Address = 0xEC50_0008 MODE_CFGn Description Reset Value CH_WIDTH [30:29] 00 = Byte 01 = Halfword...
  • Page 675 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.5 SPI Interrupt Enable Register • SPI_INT_EN0, R/W, Address = 0xEC30_0010 • SPI_INT_EN1, R/W, Address = 0xEC40_0010 • SPI_INT_EN2, R/W, Address = 0xEC50_0010 SPI_INT_ENn Description Reset Value Interrupt Enable for trailing count to be 0...
  • Page 676 S5PC100 USER’S MANUAL (REV1.0) SPI CONTROLLER 4.2.6 SPI Status Register • SPI_STATUS0, R, Address = 0xEC30_0014 • SPI_STATUS1, R, Address = 0xEC40_0014 • SPI_STATUS2, R, Address = 0xEC50_0014 SPI_STATUSn Description Reset Value Indication of transfer done in Shift register(master mode only)
  • Page 677 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.7 SPI TX Data Register • SPI_TX_DATA, W, Address = 0xEC30_0018 • SPI_TX_DATA, W, Address = 0xEC40_0018 • SPI_TX_DATA, W, Address = 0xEC50_0018 SPI_TX_DATAn Description Reset Value This field contains the data to be transmitted over the SPI...
  • Page 678 S5PC100 USER’S MANUAL (REV1.0) SPI CONTROLLER 4.2.10 Status Pending Clear Register • PENDING_CLR_REG0, R/W, Address = 0xEC30_0024 • PENDING_CLR_REG1, R/W, Address = 0xEC40_0024 • PENDING_CLR_REG2, R/W, Address = 0xEC50_0024 PENDING_CLR_REGn Description Reset Value TX underrun pending clear bit TX_UNDERRUN_CLR 0 = Non-Clear...
  • Page 679 SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2.11 SWAP Config Register • SWAP_CFG_REG0, R/W, Address = 0xEC30_0028 • SWAP_CFG_REG1, R/W, Address = 0xEC40_0028 • SWAP_CFG_REG2, R/W, Address = 0xEC50_0028 SWAP_CFGn Description Reset Value RX_HWORD_SWAP 0 = Off 1 = Swap RX_BYTE_SWAP...
  • Page 680 INFRARED DATA ASSOCIATION CONTROLLER 1 OVERVIEW The Samsung Infrared Data association (IrDA) Core is a wireless serial communication controller. It supports two different types of IrDA speed (MIR, FIR). This core transmits Infrared pulses at the high speed rate, 4 Mbps. It includes configurable FIFO feature to reduce the CPU burden.
  • Page 681 IRDA S5PC100 USER’S MANUAL (REV1.0) 3 BLOCK DIAGRAM INTERRUPT, DMA MASTER_Control Iinterrupt Control and payload length store SCLK_IRDA(48MHz) CLK_GEN ACREG HRESETn RXFLH RXFLL TXFLH TXFLL IRSDBW AHB BUS TX FIFO Control TX FIFO FIR Mod/Demodl IRRX DEMOD RX FIFO Control...
  • Page 682 S5PC100 USER’S MANUAL (REV1.0) IRDA 4 FUNCTION DESCRIPTION 4.1 FAST-SPEED INFRARED (FIR) MODE (IRDA 1.1) In this FIR mode, data communicates at the baud rate speed of 4 Mbps. In the data transmission mode, the core encodes the payload data into 4PPM format and attaches the Preamble, Start Flag, CRC-32, and Stop flag on the encoded payload and shifts them out serially.
  • Page 683 IRDA S5PC100 USER’S MANUAL (REV1.0) Enable ~ena Preamble Transmit pre_end Start Flag Transmit str_end apeend Pay Load abort by Frame data ~abort Transmit underrun with error & CRC pay_end Transmit crc_end Stop Flag Pulse Transmit transmit stp_end & ena pul_end & ena stp_end &...
  • Page 684 S5PC100 USER’S MANUAL (REV1.0) IRDA ~(ena & prebyte) Enable ena & prebyte Preamble & start flag Detect str_end Pay Load phy_err Detect & 4ppm decod crc_decod_start Pay Load Detect & CRC check pay_end = last_byte Decoding for syndrom stp_start Stop...
  • Page 685 IRDA S5PC100 USER’S MANUAL (REV1.0) 4.2 MEDIUM-SPEED INFRARED (MIR) MODE (IRDA 1.1) In MIR mode, data communicates at the speed of 1.152Mbps, and 0.576Mbps (half mode). The payload data is wrapped around by Start Flags, CRC-16, and Stop Flags. The Start Flag should be at least 2 bytes. To transmit and receive, the basic wrapping and de-wrapping processes are same as FIR mode, but, the MIR mode needs the bit-stuffing procedure.
  • Page 686 S5PC100 USER’S MANUAL (REV1.0) IRDA Enable ~ena ACREG[7] 1st Start Flag Transmit str_end append Pay Load abort by Frame data ~abort Transmit underrun with error with stuff bit crc & eflag pay_end Transmit with stuff bit crc_end Stop Flag Pulse...
  • Page 687 IRDA S5PC100 USER’S MANUAL (REV1.0) ~(ena&flagbyte) Enable ena & flagbyte Str Flag Detect str_end Pay Load Detect & De-Stuff pay_end CRC check & Stp Det stp_end Figure 8.4-6 MIR Demodulation Process Figure 8.4-6 shows the MIR demodulation state machine. Basically, it has similar structure with FIR demodulation state machine.
  • Page 688 S5PC100 USER’S MANUAL (REV1.0) IRDA 4.3 CORE INITIALIZATION PROCEDURE 4.3.1 MIR/FIR Mode Initialization Operation 1. Program the MDR register to select the MIR/ FIR mode. 2. Program the ACR register to select the transceiver type. • For the Temic-IBM type transceiver, program twice in ACR[0] = 1'b0 and ACR[0] = 1'b1.
  • Page 689 IRDA S5PC100 USER’S MANUAL (REV1.0) 5 I/O DESCRIPTION Table 8.4-1 IrDA signals Function Signal Description Type IrDA_RXD Input IrDA Rx signal XuTXD[3] Muxed IrDA_TXD Output IrDA Tx signal XuRXD[3] Muxed IrDA Transceiver control IrDA_SDBW Output XuCLK Muxed (Shutdown, Bandwidth) NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals.
  • Page 690 S5PC100 USER’S MANUAL (REV1.0) IRDA 6 REGISTER DESCRIPTION Register Address Description Reset Value IrDA _CNT 0xEC60_0000 IrDA Control Register 0x00 IrDA_MDR 0xEC60_0004 IrDA Mode Definition Register 0x00 IrDA_CNF 0xEC60_0008 IrDA Interrupt / DMA Configuration Register 0x00 IrDA _IER 0xEC60_000C IrDA Interrupt Enable Register...
  • Page 691 IRDA S5PC100 USER’S MANUAL (REV1.0) 6.1 IRDA CONTROL REGISTER(IRDA_CNT, R/W, ADDRESS = 0XEC60_0000) IrDA _CNT Description Initial State TX Enable Enables TX. Bit 7 must be set to '1' to enable data transmission in MIR/FIR infrared modes. RX Enable Enables RX. Bit 6 must be set to '1' to enable data receive in all MIR/FIR infrared modes.
  • Page 692 S5PC100 USER’S MANUAL (REV1.0) IRDA 6.3 IRDA INTERRUPT / DMA CONFIGURATION REGISTER (IRDA_CNF, R/W, ADDRESS = 0XEC60_0008) IrDA _CNF Description Initial State Reserved [7:4] DMA Enable 1 : DMA Enable DMA Mode 0 : Tx DMA 1 : Rx DMA...
  • Page 693 IRDA S5PC100 USER’S MANUAL (REV1.0) 6.5 IRDA INTERUPT IDENTIFICATION REGISTER(IRDA_IIR, R, ADDRESS = 0XEC60_0010) IrDA _IIR Description Initial State Last Byte to Rx Last byte write to RX FIFO interrupt pending. If the last payload FIFO byte of the frame is loaded into the RX FIFO, bit 7 is set to '1'. Bit 7 is set prior to bit 2.
  • Page 694 S5PC100 USER’S MANUAL (REV1.0) IRDA 6.6 IRDA LINE STATUS REGISTER(IRDA_LSR, R, ADDRESS = 0XEC60_0014) IrDA_LSR Description Initial State Tx Empty Transmitter empty. This bit is set to '1' if TX FIFO is empty and the transmitter front-end is idle. Reserved Received Last Last byte received from RX FIFO.
  • Page 695 IRDA S5PC100 USER’S MANUAL (REV1.0) 6.7 IRDA FIFO CONTROL REGISTER(IRDA_FCR, R/W, ADDRESS = 0XEC60_0018) IrDA _FCR Description Initial State Rx FIFO Trigger [7:6] Receiver FIFO trigger level selection. Level Select Bit 7 Bit 6 64-byte RX FIFO FIFO Size Select Must set to '1', to use 64 bytes TX and RX FIFO.
  • Page 696 S5PC100 USER’S MANUAL (REV1.0) IRDA 6.8 IRDA PREAMBLE LENGTH REGISTER(IRDA_PLR, R/W, ADDRESS = 0XEC60_001C) REG_PLR Description Initial State Preamble Length [7:6] These two bits decide preamble length to be transmitted at the beginning of each frame in FIR mode. The default value of in FIR mode PLR[7:6] = '00' which is equal to 16 preambles.
  • Page 697 IRDA S5PC100 USER’S MANUAL (REV1.0) 6.12 IRDA TRANSMIT FRAME-LENGTH REGISTER LOW(IRDA_TXFLL, R/W, ADDRESS = 0XEC60_002C) IrDA _TXFLL Description Initial State Tx frame length low [7:0] TXFLL stores the lower 8 bits of the byte number of the frame to be transmitted.
  • Page 698 S5PC100 USER’S MANUAL (REV1.0) CCAN C_CAN 1 OVERVIEW The C_CAN is a CAN module integrated as stand-alone device or as part of an ASIC. It is described in VHDL on RTL level, prepared for synthesis. It consists of the components namely (see Figure 8.5-1) CAN Core, Message RAM, Message Handler, Control Registers, and Module Interface.
  • Page 699 CCAN S5PC100 USER’S MANUAL (REV1.0) BLOCK DIAGRAM The design consists of the functional blocks described below (see Figure 8.5-1): CAN Core CAN Protocol Controller and Rx/Tx Shift Register for serial/ parallel conversion of messages. Message RAM Stores Message Objects and Identifier Masks.
  • Page 700: Operation Modes

    S5PC100 USER’S MANUAL (REV1.0) CCAN Figure 8.5-1 Block Diagram of the C_CAN 4 OPERATION MODES 4.1 SOFTWARE INITIALISATIOIN The software initialization is started by setting the bit Init in the CAN Control Register, either by software or by a hardware reset, or by going Bus_Off.
  • Page 701 CCAN S5PC100 USER’S MANUAL (REV1.0) The initialization of the Message Objects is independent of Init and is done on the fly, but the Message Objects should be configured to particular identifiers or set to not valid before the BSP starts the message transfer.
  • Page 702 S5PC100 USER’S MANUAL (REV1.0) CCAN 4.1.3 Test Mode Set Test bit to 1 in the CAN Control Register to enter Test Mode. In Test Mode the bits Tx1, Tx0, LBack, Silent and Basic in the Test Register are writable. Bit Rx monitors the state of pin CAN_RX and therefore is only readable.
  • Page 703 CCAN S5PC100 USER’S MANUAL (REV1.0) 4.1.6 Loop Back combined with Silent Mode It is also possible to combine Loop Back Mode and Silent Mode by programming bits LBack and Silent to one at the same time. This mode is used for a "Hot Selftest", meaning the C_CAN is tested without affecting a running CAN system connected to the pins CAN_TX and CAN_RX.
  • Page 704 S5PC100 USER’S MANUAL (REV1.0) CCAN 4.1.8 Software control of pin CAN_TX Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its default function, the serial data output, drives the CAN Sample Point signal to monitor CAN_Core's bit timing and drives constant dominant or recessive values.
  • Page 705 CCAN S5PC100 USER’S MANUAL (REV1.0) The structure of the APB2 interface is shown is Figure 8.5-5. Figure 8.5-5 Structure of the C_CAN with APB2 Interface 8. 5-8...
  • Page 706 S5PC100 USER’S MANUAL (REV1.0) CCAN If there is a write access, the registers CAN_ADDR and CAN_DATA_IN store the actual address PADDR and write data PWDATA clocked with PCLK. Additionally the flip-flop TOGGLE_WR is toggled. The flips-flops TOGGLE_WR, WR_TOGGLE1 and WR_TOGGLE2 describe a shift register, where TOGGLE_WR is clocked by PCLK, WR_TOGGLE1 and WR_TOGGLE2 are clocked by CAN_CLK.
  • Page 707 CCAN S5PC100 USER’S MANUAL (REV1.0) A read access to the C_CAN module with APB2 interface must be performed as "double read". With the first read, the requested data is written into the internal register (SYNC_PRDATA) clocked by CAN_CLK. With the second read the data output register PRDATA takes over the value of SYNC_PRDATA (see Figure 8.5-7).
  • Page 708 S5PC100 USER’S MANUAL (REV1.0) CCAN 5 I/O DESCRIPTION Table 8.5-1 CCAN Signals Function Signal Description Type CAN0_TX Output CCAN0 TX Data XEINT[28] Muxed CAN0_RX Input CCAN0 RX Data XEINT[29] Muxed CAN1_TX Output CCAN1 TX Data XEINT[30] Muxed CAN1_RX Input CCAM1 RX Data...
  • Page 709 CCAN S5PC100 USER’S MANUAL (REV1.0) 6 REGISTER DESCRIPTION The C_CAN module allocates an address space of 256 bytes. The registers are organized as 16-bit registers, with the high byte at the odd address and the low byte at the even address.
  • Page 710 S5PC100 USER’S MANUAL (REV1.0) CCAN Register Address Description Reset Value CAN_IF2_DA1 0xEC70_009C IF2 Data A 1 0x0000 CAN_IF2_DA2 0xEC70_00A0 IF2 Data A 2 0x0000 CAN_IF2_DB1 0xEC70_00A4 IF2 Data B 1 0x0000 CAN_IF2_DB2 0xEC70_00A8 IF2 Data B 2 0x0000 0xEC70_00AC Reserved...
  • Page 711 CCAN S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value CAN_IF1_MC 0xEC80_0038 IF1 Message Control 0x0000 CAN_IF1_DA1 0xEC80_003C IF1 Data A 1 0x0000 CAN_IF1_DA2 0xEC80_0040 IF1 Data A 2 0x0000 CAN_IF1_DB1 0xEC80_0044 IF1 Data B 1 0x0000 CAN_IF1_DB2 0xEC80_0048 IF1 Data B 2...
  • Page 712 S5PC100 USER’S MANUAL (REV1.0) CCAN The two sets of Message Interface Registers − IF2 and IF2 − have identical functions. Reserved bits are read as '0' except for IFx Mask 2 Register where they are read as '1'. All reserved bits are read only.
  • Page 713 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2 DETAILED DESCRIPTION These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the configuration of the CAN bit timing and provide status information. 6.2.1 CAN Control Register •...
  • Page 714 S5PC100 USER’S MANUAL (REV1.0) CCAN During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the Status Register. This enables the CPU to readily check whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the busoff recovery sequence.
  • Page 715 CCAN S5PC100 USER’S MANUAL (REV1.0) CANn_STS Description Reset Value 100 = Bit1Error : During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the...
  • Page 716 S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.4 Bit timing Register • CAN0_BT, R/W, Address = 0xEC70_000C • CAN1_BT, R/W, Address = 0xEC80_000C CANn_BT Description Reset Value Reserved [15] Reserved TSeg2 [14:12] The time segment after the sample point 0x0-0x7: valid values for TSeg2 are [0..7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
  • Page 717 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2.5 Interrupt Register • CAN0_INTR, R/W, Address = 0xEC70_0010 • CAN1_INTR, R/W, Address = 0xEC80_0010 CANn_INTR Description Reset Value IntID15-0 [15:0] Interrupt Identifier (the number here indicates the source of the interrupt) 0x0000: No interrupt is pending...
  • Page 718: X9000

    S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.7 BRP Extension Register • CAN0_BRP, R/W, Address = 0xEC70_0018 • CAN1_BRP, R/W, Address = 0xEC80_0018 CANn_BRP Description Reset Value Reserved [15:4] Reserved BRPE [3:0] Baud Rate Prescaler Extension 0x00-0x0F: By programming BREP the Baud Rate Prescaler is extended to values up to 1023.
  • Page 719 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2.9 IF1 Command Request Register • CAN0_IF1, R/W, Address = 0xEC70_0020 • CAN1_IF1, R/W, Address = 0xEC80_0020 6.2.10 IF2 Command Request Register • CAN0_IF2, R/W, Address = 0xEC70_0080 • CAN1_IF2, R/W, Address = 0xEC80_0080 CANn_IF1...
  • Page 720 S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.12 IF2 Command Mask Register • CAN0_IF2_CM, R/W, Address = 0xEC70_0084 • CAN1_IF2_CM, R/W, Address = 0xEC80_0084 CANn_IF1_CM Description Reset Value CANn_IF2_CM Reserved [15:8] Reserved WR/RD Write / Read 1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
  • Page 721 CCAN S5PC100 USER’S MANUAL (REV1.0) CANn_IF1_CM Description Reset Value CANn_IF2_CM 1 = Set TxRqst bit 0 = TxRqst bit unchanged If (Direction = Read) 1 = Clear NewDat bit in the Message Object 0 = NewDat bit remains unchanged Data A...
  • Page 722 S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.16 IF2 Mask 2 Register • CAN0_IF2_M2, R/W, Address = 0xEC70_008C • CAN1_IF2_M2, R/W, Address = 0xEC80_008C CANn_IF1_M2 Description Reset Value CANn_IF2_M2 MXtd [15] Mask Extended Identifier 1 = The extended identifier bit (IDE) is used for acceptance filtering.
  • Page 723 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2.17 IF1 Arbitration 1 Register • CAN0_IF1_A1, R/W, Address = 0xEC70_0030 • CAN1_IF1_A1, R/W, Address = 0xEC80_0030 6.2.18 IF2 Arbitration 1 Register • CAN0_IF2_A1, R/W, Address = 0xEC70_0090 • CAN1_IF2_A1, R/W, Address = 0xEC80_0090 CANn_IF1_A1...
  • Page 724 S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.20 IF2 Arbitration 2 Register (CAN_IF2_A2, R/W, Address = 0xEC70_0094, 0xEC80_0094) • CAN0_IF2_A2, R/W, Address = 0xEC70_0094 • CAN1_IF2_A2, R/W, Address = 0xEC80_0094 CANn_IF1_A2 Description Reset Value CANn_IF2_A2 MsgVal [15] Message Valid 1 = The Message Object is configured and should be considered by the Message Handler.
  • Page 725 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2.21 IF1 Message Control Register (CAN_IF1_MC, R/W, Address = 0xEC70_0038, 0xEC80_0038) • CAN0_IF1_MC, R/W, Address = 0xEC70_0038 • CAN1_IF1_MC, R/W, Address = 0xEC80_0038 6.2.22 IF2 Message Control Register (CAN_IF2_MC, R/W, Address = 0xEC70_0098, 0xEC80_0098) •...
  • Page 726 S5PC100 USER’S MANUAL (REV1.0) CCAN CANn_IF1_MC Description Reset Value CANn_IF2_MC 0 = At the reception of a Remote Frame, TxRqst is left unchanged TxRqst Transmit Request 1= The transmission of this Message Object is requested and is not yet done.
  • Page 727 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2.25 IF1 Message Data A2 (CAN_IF1_DA2, R/W, Address = 0xEC70_0040, 0xEC80_0040) • CAN0_IF1_A2, R/W, Address = 0xEC70_0040 • CAN1_IF1_A2, R/W, Address = 0xEC80_0040 6.2.26 IF2 Message Data A2 (CAN_IF2_DA2, R/W, Address = 0xEC70_00A0, 0xEC80_00A0) •...
  • Page 728 S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.29 IF1 Message Data B2 (CAN_IF1_DB2, R/W, Address = 00EC70_0048, 0xEC80_0048) • CAN0_IF1_DB2, R/W, Address = 0xEC70_0048 • CAN1_IF1_DB2, R/W, Address = 0xEC80_0048 6.2.30 IF2 Message Data B2 (CAN_IF2_DB2, R/W, Address = 00EC70_00A8, 0xEC80_00A8) •...
  • Page 729 CCAN S5PC100 USER’S MANUAL (REV1.0) 6.2.33 New Data Register 1 (CAN_ND1, R, Address = 00EC70_0120, 0xEC80_0120) • CAN0_ND1, R/W, Address = 0xEC70_0120 • CAN1_ND1, R/W, Address = 0xEC80_0120 CANn_ND1 Description Reset Value NewDat16-1 [15:0] New Data Bits (of all Message Objects)
  • Page 730 S5PC100 USER’S MANUAL (REV1.0) CCAN 6.2.36 Interrupt Pending Register 2 (CAN_IntPen2, R, Address = 00EC70_0144, 0xEC80_0144) • CAN0_IntPen2, R/W, Address = 0xEC70_0144 • CAN1_IntPen2, R/W, Address = 0xEC80_0144 CANn_IntPen2 Description Reset Value IntPnd32-17 [15:0] Interrupt Pending Bits (of all Message Objects) 1 = This message object is the source of an interrupt.
  • Page 731 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER MIPI HSI INTERFACE CONTROLLER 1 OVERVIEW MIPI HSI is a high speed synchronous serial interface and is defined for communication between two ICs. The targeted scenario is an application IC and cellular modem IC communication. Data transaction model is peer-to- peer.
  • Page 732 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) FEATURES The MIPI HSI Rx/ Tx controller features: The MIPI HSI interface is uni-direction interface. MIPI HSI maximum bandwidth is 200Mbps. The MIPI HSI Tx controller use PCLK for data transmitting. Tx Module: •...
  • Page 733 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER Rx Module: • Status Register ♦ FIFO status (fifo full, fifo empty, fifo write point, fifo read point) ♦ Sks..MIPI status (Internal status: Current status and Next status) • Configuration Register 0 ♦...
  • Page 734 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3 BLOCK DIAGRAM 3.1 TOP-LEVEL BLOCK DIAGRAM Rx module part and Tx module part basic architecture is similar. MIPI MTx_Data APB BUS MTx_Flag MIPI module MTx_Wake Data Parallel FIFO MRx_Ready (32bits width)
  • Page 735 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 3.1.1 Tx Module Part Parallel-to-Serial Block A top-level block diagram of the PC card controller is shown below in Figure 8.6-5. FLAG Flag D == PRE_D? Data PCLK DATA Data Figure 8.6-5 Parallel -to- Serial Block (Tx Module Part)
  • Page 736 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.1.2 Rx Module Part Serial-to-Parallel Block A top-level block diagram of the ATAPI controller is shown below in Figure 8.6-6. Rising-edge shift counter DATA FLAG Falling-edge shift counter Figure 8.6-6 Serial-to-Parallel Block (Rx Module Part)
  • Page 737 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 4 CLOCK SCHEME 4.1 TX MODULE PART PARALLEL-TO-SERIAL BLOCK FLAG Flag D == PRE_D? Data PCLK DATA Data Figure 8.6-7 Parallel-to-Serial Block (Tx Module Part) 8.6-7...
  • Page 738 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2 RX MODULE PART : SERIAL-TO-PARALLEL BLOCK Rising-edge shift counter DATA FLAG Falling-edge shift counter Figure 8.6-8 Serial-to-Parallel Block (Rx Module Part) 8.6-8...
  • Page 739 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER TIMING DIAGRAM 5.1 WAVEFORM Figure 8.6-9 Waveform 5.2 SIGNAL TIMINGS Table 8.6-1 Signal Timings Parameter Description 1 Mbit/s 100 Mbit/s 200 Mbit/s TNomBit Nominal bit time 1000 ns 10 ns 5 ns...
  • Page 740 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.3 SINGLE/BURST CHANNEL ID MODE < Stream mode > < Frame mode > Figure 8.6-10 Example of Burst Channel ID Mode If HSI is in Single channel ID mode, it attaches channel ID to each data whenever HSI transfers data. If HSI is in Burst channel ID mode, it attaches channel ID to beginning of data frame and transfers 32-bit data before it enters IDLE state.
  • Page 741 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 5.5 FRAME MODE 5.5.1 Normal Mode Figure 8.6-12 Example of Frame Mode (Normal Mode) 5.5.2 Break Frame Figure 8.6-13 Break Frame Flag line toggles until the transfer is end if Break frame transfers at least 36 zeros. Tx module transferring Break frame does not require to monitor the ready signal unlike normal mode.
  • Page 742 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 6 I/O DESCRIPTION Table 8.6-2 I/O Description Function Signal Description Type MIPI HSI interface Signals (Tx) HSI_TXD MIPI HSI data line XmsmA[0] Muxed HSI_TX_FLAG MIPI HSI flag line XmsmA[1] Muxed HSI_TX_WAKE MIPI HSI wake up line to the other side Rx...
  • Page 743 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 8.6-13...
  • Page 744 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7 REGISTER DESCRIPTION 7.1 REGISTER MAP TABLE Table 8.6-3 Tx Controller Register Map Table Register Address Description Reset Value STATUS_REG 0xEC90_0000 MIPI HSI Tx Controller Status Register 0x00010000 CONFIG_REG 0xEC90_0004 MIPI HSI Tx Controller Configuration Register...
  • Page 745 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 8 INDIVIDUAL REGISTER DESCRIPTIONS (TX CONTROLLER) 8.1 MIPI HSI RX CONTROLLER STATUS REGISTER (STATUS_REG, R, ADDRESS = 0XEC90_0000) STATUS_REG Description Reset Value reserved [31] next_state [30:28] Next state* reserved [27] current state...
  • Page 746 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 8.2 MIPI HSI TX CONTROLLER CONFIGURATION REGISTER(CONFIG_REG, R/W, ADDRESS = 0XEC90_0004) CONFIG_REG Description Reset Value TxHOLD time [31:24] TxHOLD state timer setting value 0xFF TxIDLE time [23:16] TxIDLE state timer setting value...
  • Page 747 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 8.3 MIPI HSI TX CONTROLLER INTERRUPT SOURCE REGISTER(INTSRC_REG, R/W, ADDRESS = 0XEC90_000C) INTSRC_REG Bits Description Reset Value Reserved [31:5] 0x0000001 TxH_timeout TxHOLD state timeout interrupt (set '1' to clear) TxI_timeout TxIDLE state timeout interrupt (set '1' to clear)
  • Page 748 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 8.5 TX CONTROLLER SOFTWARE RESET (SWRST_REG, R/W, ADDRESS = 0XEC90_0014) SWRST_REG Description Reset Value Reserved [31:1] 0x00000000 Sw_rst Software reset 0 : Set 1 : Reset 8.6 MIPI HSI TX CONTROLLER CHANNEL ID REGISTER (CHID_REG, R/W, ADDRESS = 0XEC90_0018)
  • Page 749 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 8.8 MIPI HSI RX CONTROLLER STATUS REGISTER (STATUS_REG, R, ADDRESS = 0XECA0_0000) STATUS_REG Description Reset Value Reserved [31] Next_state [30:28] Next state* Reserved [27] Curr_state [26:24] Current state* Reserved [23:19] 0x00 FIFO_timeout...
  • Page 750 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 8.9 MIPI HSI RX CONTROLLER CONFIGURATION REGISTER (CONFIG0_REG, R/W , ADDRESS = 0XECA0_0004) CONFIG0_REG Description Reset Value Reserved [31:30] DREQ_thres_val [29:28] DMA request threshold value 0x00 DMA request signal is active if valid data in FIFO is...
  • Page 751 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 8.10 MIPI HSI RX CONTROLLER CONFIGURATION REGISTER (CONFIG1_REG, R/W, ADDRESS = 0XECA0_0008) CONFIG1_REG Description Reset Value RxFIFO_clr [31] Break frame receiving timer setting value Reserved [30:28] RxFIFO_timer_en [27] Enables RxFIFO timer Reserved...
  • Page 752 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 8.12 MIPI HSI RX CONTROLLER INTERRUPT MASK REGISTER (INTMSK_REG, R/W, ADDRESS = 0XECA0_0010) INTMSK_REG Description Reset Value DMA_req_en [31] Enable DMA request signal 0: Enables 1: Disables Reserved [30:10] 0x1fffff RxWakeup_msk Enables RX Wake-up Interrupt...
  • Page 753 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 8.13 RX CONTROLLER SOFTWARE RESET (SWRST_REG, R/W, ADDRESS = 0XECA0_0014) SWRST_REG Description Reset Value Reserved [31:1] 0x00000000 Sw_rst Software reset 0 : Set 1 : Reset 8.14 MIPI HSI RX CONTROLLER CHANNEL ID REGISTER (CHID_REG, R, ADDRESS = 0XECA0_0018)
  • Page 754 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) PROGRAMMING GUIDE 9.1 BASIC DRAWING FUNCTION 9.1.1 Tx Module Programming Guide Flow Chart Start Put the channel ID Put the Data at FIFO Change Channel ID ? FIFO full ? FIFO empty ?
  • Page 755 S5PC100 USER’S MANUAL (REV1.0) MIPI HSI INTERFACE CONTROLLER 9.1.2 Rx Module Programming Guide Flow Chart Start Wait interrupt (RxDONE || FIFO full || FIFO time out)? Read channel ID reg. Read Data FIFO FIFO empty ? Figure 8.6-15 Basic Rx Module Programming Flow Chart...
  • Page 756 MIPI HSI INTERFACE CONTROLLER S5PC100 USER’S MANUAL (REV1.0) NOTES 8.6-26...
  • Page 757 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM MIPI DSIM 1 ARCHITECTURE FEATURES The MIPI DSIM features include: • Compliant to MIPI DSI Standard Specification V1.01r02 ♦ Maximum resolution range: up to XGA (1028x768) ♦ Supports 1, 2 or 3 data lanes.
  • Page 758 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) BLOCK DIAGRAM 1.2.1 Total System Block Diagram FIMD4.0 VTIME_ VTIME_i Local FIFO I / F (8 bit * 3) TVENC CLKlane _ VD Master MIPI DATlane0 _ VD DATlane1 Master block DATlane2 SFRFIL Slave I / F APB I/F Figure 8.7-1 MIPI DSI System Block Diagram...
  • Page 759 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 1.2.2 MIPI DSI Master & D-PHY I/F Block Diagram RMS[19:0] EscRef D-PHY EXTCLK ByteCLK/8 RGB I/F BandCtrl[3:0] I80 I/F BitClkHS TxByteClkHS TxRequestHSClk TxReadyHSClk TxClkEscClk Clock TxUlpsClk TxUlpsExitClk Lane UlpsAcitveNotClk StopstateClk EnableClk MIPI TxByteClkHS TxRequestHS...
  • Page 760 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 1.2.3 Internal Primary FIFOs There are some configurable-sized primary FIFOs. Table 8.7-1 describes these primary FIFOs. Table 8.7-1 Internal Primary FIFO list Port FIFO type Size Description Main display Packet Header FIFO 3byte X 64 depth...
  • Page 761 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 1.2.4 Packet Header Arbitration There are four-packet headers FIFOs for Tx: Main display, Sub display, I80 I/F command and SFR FIFO. Main and sub display packet header FIFO transfers image data. I80 I/F command packet header FIFO transfers command packets.
  • Page 762 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) INTERFACES & PROTOCOL 1.3.1 Display Controller-to-DSI Conceptual Signal Converting Diagram in Video Mode RGB_VSYNC RGB_HSYNC RGB_VDEN RGB_DATA DSI_channel BLLP BLLP BLLP BLLP BLLP BLLP BLLP BLLP Vsync start packet BLLP Burst mode Vsync end packet...
  • Page 763 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 1.3.2 Interface Timing and Protocol 1.3.2.1 Display Controller Interface MIPI DSI Master has two-display controller interface: RGB I/F for main display and CPU I/F (I80 I/F) for main/sub display. Video mode uses RGB I/F,and Command mode uses CPU I/F.
  • Page 764 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 1.3.2.4 HBP Mode HBP mode is Horizontal Back Porch disable mode. Burst mode BLLP BLLP (HBPmode) Non burst mode with Sync event (HBPmode) Non burst mode with Sync pulses (HBPmode) Hsync start packet Hsync end packet Figure 8.7-7 Block Timing Diagram of HBP mode (HBP Mode Reset : DSIM_CONFIG[21] = 0)
  • Page 765 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 1.3.2.5 HFP mode HFP mode is Horizontal Front Porch disable mode. Burst mode BLLP BLLP (HFPmode) Non burst mode with Sync event (HFmode) Non burst mode with Sync pulses (HFPmode) Hsync start packet Hsync end packet Figure 8.7-94 Block Timing Diagram of HFP mode (HFP Mode Reset : DSIM_CONFIG[22] = 0)
  • Page 766 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 1.3.2.6 HSE mode HSE mode is Horizontal Sync End packet enable mode in Vsync pulse or Vporch area. Non burst mode with Sync pulses BLLP BLLP (HSAmode) Vsync pulse or Vporch area DSI_channel BLLP...
  • Page 767 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 1.3.2.7 Transfer General Data in Video Mode Vsync Command masked area (VBP + active region) Stable VFP area (register configuration) Vsync Command masked area Only this area can be started (protecting Vsync start) command through LPDT or HS (register configuration) Figure 8.7-13 Stable VFP Area Before Command Transfer Allowing Area...
  • Page 768 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 1.3.2.8 I80 I/F clock SYS_CS0/CS1 SYS_WE SYS_VD[23:0] Figure 8.7-14 I80 I/F Timing Diagram T1 ≥ 1 clock cycle. T2 ≥ 0 clock cycle. T3 ≥ 1 clock cycle. T4 ≥ 1 clock cycle. T5 ≥ 2 clock cycle.
  • Page 769 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM I80 I/F Input Command mode output . . . P(h-1) Payload . . . (DCS command is P(h) P(h+1) P(h+2) P(2h-1) (DCS long (CRC ) write) “write_memory_start”) Payload . . . (DCS command is...
  • Page 770 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 1.3.2.9 Relation between Input Transactions and DSI Transactions Table 8.7-3 Relation between input transactions and DSI transactions Input Interface Input transaction DSI Transaction RGB transaction RGB Packet 888,666,666(loosely packed), 565 should be specified via...
  • Page 771 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 2 I/O DESCRIPTION Table 8.7-4 MIPI-DPHY interface Slave Signal Function Signal Description Type MIPI_DP_0 DP signal for MIPI-DPHY Master data-lane 0 XmipiDP[0] dedicated MIPI_DN_0 DN signal for MIPI-DPHY Master data-lane 0 XmipiDN[0] dedicated MIPI_DP_1...
  • Page 772 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3 REGISTER DESCRIPTION 3.1 REGISTER OVERVIEW Register Address Description Reset Value DSIM_STATUS 0xECB0_0000 Status register 0x0010_010F DSIM_SWRST 0xECB0_0x04 Software reset register 0x0000_0000 DSIM_CLKCTRL 0xECB0_0x08 Clock control register 0x0000_FFFF DSIM_TIMEOUT 0xECB0_0x0C Time Out register 0x00FF_FFFF...
  • Page 773 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 3.2 DETAILED DECRIPTION 3.2.1 Status Register (DSIM_STATUS, R, Address = 0xECB0_0000) This registers reads and checks status Internal & interface status. FSM status, Line buffer status, current image line number, etc. DSIM_STATUS Description Reset Value...
  • Page 774 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.2 Software Reset Register (DSIM_SWRST, R/W, Address = 0xECB0_0x04) DSIM_SWRST Description Reset Value Reserved [31:17] Reserved FuncRst [16] Software reset (High active). "Software reset" reset all of FF in MIPI DSIM (except SFRs: STATUS, SWRST,...
  • Page 775 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM DSIM_CLKCTRL Description Reset Value ByteClkSrc [26:25] Byte clock source selection 00 = D-PHY PLL (default) 01 = External Bit clock source and ByteClk source by dividing by 4. 1X = External clock bypass to ByteClk If you want to change clock source, turn off D-PHY PLL before changing clock source.
  • Page 776 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.4 Time Out register (DSIM_TIMEOUT, R/W, Address = 0xECB0_0x0C) DSIM_TIMEOUT Description Reset Value Reserved [31:24] Reserved BtaTout [23:16] Timer for BTA 0xFF This register specifies time out from BTA request to change the direction with respect to Tx escape clock.
  • Page 777 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM DSIM_CONFIG Description Reset Value AutoMode [24] Auto vertical count mode In Video mode, Vertical line transition use line counter configured by VSA, VBP and Vertical resolution. If this bit is set to '1', line counter does not use VSA and VBP registers.
  • Page 778 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) DSIM_CONFIG Description Reset Value MainPixFormat [14:12] Pixel stream format for main display 000 = 3bpp for Command mode only 001 = 8bpp for Command mode only 010 = 12bpp for Command mode only 011 = 16bpp for Command mode only...
  • Page 779 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 3.2.6 Escape Mode Register (DSIM_ESCMODE , R/W, Address = 0xECB0_0x14) This register configures MIPI DSI master. DSIM_ESCMODE Description Reset Value STOPstate_Cnt [31:21] After transmitting read packet or write "set_tear_on" command, BTA request to D-phy automatically. This counter value is the interval value between transmitting read packet (or write "set_tear_on"...
  • Page 780 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.7 Main Display Image Resolution Register (DSIM_MDRESOL, R/W, Address = 0xECB0_0x18) DSIM_MDRESOL Description Reset Value MainStandby [31] Standby for receiving DISPCON output in Command mode after setting all configuration 0 = Not ready 1 = Stand by Standby should be set after configuration (resolution, reqtype, pixelform, etc.) is set for command mode.
  • Page 781 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 3.2.9 Main display Hporch register (DSIM_MHPORCH, R/W, Address = 0xECB0_0x20) DSIM_MHPORCH Description Reset Value MainHfp[15:0] [31:16] Horizontal Front Porch width for Video mode HFP is specified using along blank packet. These bits are word counts for blank packet in HFP.
  • Page 782 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.12 Interrupt Source Register (DSIM_INTSRC, R/W, Address = 0xECB0_0x2C) This register identifies interrupt sources. Internal block error, data transmit interrupt, inter-layer( D_PHY) error, etc. The bits are set even if they are masked off by DSIM_INTMSK_REG.
  • Page 783 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM DSIM_INTSRC Description Reset Value ErrSync1 LPDT Sync Error lane1 (For more information refer to standard d-phy specification) ErrSync0 LPDT Sync Error lane0 (For more information refer to standard d-phy specification) Reserved Reserved ErrControl2 Control Error lane2...
  • Page 784 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.13 Interrupt mask register (DSIM_INTMSK, R/W, Address = 0xECB0_0x30) This register masks interrupt sources. DSIM_INTMSK Description Reset Value MskPllStable [31] Indicates that D-phy PLL is stable MskSwRstRelease [30] Software reset is released MskSFRFifoEmpty [29]...
  • Page 785 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM DSIM_INTMSK Description Reset Value (For more information refer to standard d-phy specification) Reserved Reserved MskControl2 Control Error lane2 (For more information refer to standard d-phy specification) MskControl1 Control Error lane1 (For more information refer to standard d-phy...
  • Page 786 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.16 Read FIFO register (DSIM_RXFIFO, R, Address = 0xECB0_0x3C) This register is the gate of FIFO read DSIM_RXFIFO Description Reset Value RxDat [31:0] In Rx mode, user can read Rx data through this Unknown register.
  • Page 787 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 3.2.18 FIFO Status & Control Register (DSIM_FIFOCTRL, R, Address = 0xECB0_0x44 : hidden) DSIM_FIFOCTRL Description Reset Value Reserved [31:26] Reserved FullRx [25] Rx FIFO full EmptyRx [24] Rx FIFO empty FullHSfr [23] SFR packet header FIFO full...
  • Page 788 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 3.2.19 FIFO Memory AC Characteristic Register (DSIM_MEMACCHR, R/W, Address = 0xECB0_0x48 : hidden) DSIM_MEMACCHR Description Reset Value Reserved [31:16] Reserved PGEN_SD [15] Sub display FIFO memory power gating RETN_SD [14] Sub display FIFO memory Retention...
  • Page 789 S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM 4 DPHY PLL CONTROL 4.1 PMS SETTING SAMPLE FOR MIPI PLL 4.1.1 PMS setting Write a value to PMS field in DSIM_PLLCTRL (0xECB0_004C) to set PMS value for DPHY PLL. Each P, M and S resides in PMS [19:14] , PMS[13:4] and PMS[3:1] .
  • Page 790 MIPI DSIM S5PC100 USER’S MANUAL (REV1.0) 4.1.3 Sample for Fout 1000 MHz Followings are some example to set PMS value for Fout 1000 MHz Case 1 Case 2 4MHz 80MHz Fin_pll 4MHz 4MHz P[5:0] M[9:0] S[2:0] VCO_out 1000MHz 1000MHz Fout...
  • Page 791 S5PC100 USER’S MANUAL (REV1.0) MIPI CSIS MIPI CSIS 1 OVERVIEW MIPI CSIS overall features are summarized as follows. 2 FEATURE • Compliant to MIPI CSI2 Standard Specification Version 1.0 ♦ Supports 1 or 2 data lanes ♦ Supports 1 channels ♦...
  • Page 792 MIPI CSIS S5PC100 USER’S MANUAL (REV1.0) 3 BLOCK DIAGRAM CSI 2 _RX DPSRA DPSRAM 2048 X32 D-PHY Slave CLK _GEN CLOCK _ LANE LANE _ DE _ (Slave ) DEMUX _ OUT MERGER PACKETIZER DATA _LANE 1 ERR _CONTROL 1...
  • Page 793: Data Format

    S5PC100 USER’S MANUAL (REV1.0) MIPI CSIS 5 DATA FORMAT Table 8.8-1 Data Size Constraint FORMAT Pixels Bytes Bits YUV422 8-bit RAW8 RAW10 RAW12 YUV422 8-BIT YUV422 8-bit format data is stored as a UYVY sequence. This sequence is illustrated in Figure 8.8-3.
  • Page 794 MIPI CSIS S5PC100 USER’S MANUAL (REV1.0) RAW10 10-bit RAW data is stored as the sequence illustrated in Figure 8.8-4, Table 8.8-1 specifies the data size constraints for RAW10 format. P7[7:0] P6[7:0] P5[7:0] P4[1:0] P3[1:0] P2[1:0] P1[1:0] P4[9:2] P3[9:2] P2[9:2] P1[9:2] Figure 8.8-5 RAW10 Data Storing Order...
  • Page 795 S5PC100 USER’S MANUAL (REV1.0) MIPI CSIS 6 I/O DESCRIPTION Function Signal Description Type MIPI_DP[3] DP signal for MIPI-DPHY slave data-lane 0 XmipiDP[3] Dedicated MIPI_DN[3] DN signal for MIPI-DPHY slave data-lane 0 XmipiDN[3] Dedicated MIPI_DP[4] DP signal for MIPI-DPHY slave data-lane 1...
  • Page 796 MIPI CSIS S5PC100 USER’S MANUAL (REV1.0) 7 REGISTER DESCRIPTION Register Address Description Reset Value CSIS_CONTROL 0xECC0_0000 Control Register 0x0000_0000 CSIS_DPHYCTR 0xECC0_0004 D-PHY Control Register 0x0000_0000 CSIS_CONFIG 0xECC0_0008 Configuration Register 0x0000_0000 CSIS_DPHYSTS 0xECC0_000C D-PHY STOP State Register 0x0000_0031 CSIS_INTMSK 0xECC0_0010 Interrupt Mask Register...
  • Page 797 S5PC100 USER’S MANUAL (REV1.0) MIPI CSIS D-PHY CONTROL REGISTER (CSIS_DPHYCTRL, R/W, ADDRESS = 0XECC0_0004) This register is used to control of D-phy. CSIS_DPHYCTRL Description Reset Value Reserved [31:1] Should not change the value DPHYOn Enables D-PHY Clock and Data lane...
  • Page 798 MIPI CSIS S5PC100 USER’S MANUAL (REV1.0) INTERRUPT MASK REGISTER (CSIS_INTMSK, R/W, ADDRESS = 0XECC0_0010) This register is used to mask interrupt sources. CSIS_INTMSK Description Reset Value MSK_EvenBefore [31] Non Image data are received at Even frame and Before Image 0 = Disables Interrupt...
  • Page 799 S5PC100 USER’S MANUAL (REV1.0) MIPI CSIS INTERRUPT SOURCE REGISTER (CSIS_INTSRC, R/W, ADDRESS = 0XECC0_0014) This register is used to identify interrupt sources. CSIS_INTSRC Description Reset Value EvenBefore [31] Non image data are received at even frame and before image EvenAfter...
  • Page 800 MIPI CSIS S5PC100 USER’S MANUAL (REV1.0) NOTES 8.8-10...
  • Page 801 OHCI specification2 are necessary to fully understand the material contained in this section. Refer to the Universal Serial Bus Specification Revision 1.1 and the Open HCI − Open Host controller Specification for USB for details of the interface operation. FEATURES S5PC100 supports 2-port USB host interface as follows: • OHCI Revision 1.0 compatible •...
  • Page 802 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) OPERATION 3.1 OPERATION 3.1.1 Basic Operations A USB system consists of four main components: two of these, the client software and the host controller driver, are implemented in software; the other two areas (host controller and the device controller) are implemented in hardware.
  • Page 803 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER Figure 8.9-1 Typical List Structure (Operational, resume, suspend, reset), the list processing pointers (the UHCBHDED and UHCHDED registers), list processing enables (bits 5-2 of the UHCCON register), and interrupt enables (in the UHCINTENB register).
  • Page 804 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.1.2 USB Host Controller Block Diagram OHCI ROOT HUB REGS APP_SADR(8) RCF0_RegData(32) SLAVE PORT APP_SDATA(32) BLOCK CONTROL CONTROL STATE HCI_DATA(32) CONTROL TxEnl OHCI ROOT CONTROL CONTROL REGS Cntl TxDpls PORT & LIST HOST...
  • Page 805 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 3.1.3 USB Block Diagram AHB Slave interface PHY Clock (30 Mhz) USB 2.0 PHY CONTROL Master/Slave Interface USB 2.0 OTG LINK PHY Control Signal PHY Clock (30 Mhz) (clk_sel, etc ) Crystal or Oscillator...
  • Page 806 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3.1.4 Interrupts The USB host controller generates two interrupts to the interrupt controller. • An OHCI USB interrupts (Generated from the Interrupt Status register) • All other USB host controller event interrupts ♦ Buffer-access interrupt ♦...
  • Page 807 3.2.1 USB Reset The USB host controller is not fully reset following a S5PC100 processor reset. The full-chip processor reset leaves the USB force host controller reset bit set. To initialize the USB host controller, use the following sequence: 1. Start the USB clocks 2.
  • Page 808 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4 I/O DESCRIPTION USB Host has two paths to transmit and receive data. First path is to use USB special pad and Second path is to use USB PHY. 4.1 USB PAD Funtion...
  • Page 809: Register Descriptions

    S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER REGISTER DESCRIPTIONS 5.1 REGISTER OVERVIEW Register Address Description Reset Value UHCREV 0xED40_0000 USB HcRevision Register UHCCON 0xED40_0004 USB HcControl Register UHCCONSTAT 0xED40_0008 USB HcCommandStatus Register UHCINTSTAT 0xED40_000C USB HcInterruptStatus Register UHCINTENB 0xED40_0010 USB HcInterruptEnable Register...
  • Page 810 This read-only register contains the binary-coded decimal (BCD) representation of the HCI specification version that the S5PC100 processor implements. The UHC complies with the OHCI Revision. 1.0a specification, therefore this register always has a value of 0x0000_0010. The register organization and individual bit definitions are shown in Table 8.9-2.
  • Page 811 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER Table 8.9-2 UHCCON Bit Definitions UHCCON Description Reset Value Reserved [31:11] Reserved [10] RemoteWakeupEnable The host controller driver uses this bit to enable or disable the remote wakeup feature upon the detection of upstream resume signaling.
  • Page 812 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCCON Description Reset Value HC enters USBSUSPEND after software reset, whereas it enters USBRESET after a hardware reset. The latter also resets the root hub and asserts subsequent reset signaling to downstream ports. The root hub is defined as the USB hub attached directly to the USB host controller (physically it is a part of the host).
  • Page 813 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCCON Description Reset Value processing of the periodic list does not halt until after the next SOF. UHC must check this bit before it starts processing the list. 0 = Disables processing of the periodic list.
  • Page 814 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.3 USB HcCommandStatus Register (UHCCONSTAT, Address = 0xED40_0008) The USB host controller uses the USB HOST Command Status (UHCCONSTAT, shown in Table 8.9-4) register to receive commands that the host controller driver issues, as well as reflecting the current status of the host controller.
  • Page 815 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCCONSTAT Description Reset Value BulkListFilled This bit indicates whether there are any TDs on the bulk list. It is set by the host controller driver whenever it adds a TD to an ED in the bulk list. If UHC begins to process the head of the bulk list, it checks the BulkListFilled bit (BLF).
  • Page 816 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 8.9-16...
  • Page 817 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 5.2.4 USB HcInterruptStatus Register (UHCINTSTAT, Address = 0xED40_000C) The USB INTerrupt STATus (UHCINTSTAT) register provides status on various events that cause hardware interrupts. If an event occurs, the host controller sets the corresponding bit in this register. If a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register and the MasterInterruptEnable bit is set.
  • Page 818 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCINTSTAT Description Reset Value UnrecoverableError R/WC This bit is set if UHC detects a system error not related to USB. UHC must not proceed with any processing or signaling before the system error has been corrected.
  • Page 819 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 5.2.5 USB HcInterruptEnable Register (UHCINTENB, R/W, Address = 0xED40_0010) Each enable bit in the UHC Interrupt Enable (UHCINTENB) register corresponds to an associated interrupt bit in the UHCINTSTAT register. The UHC Interrupt Enable register controls which events generate OHCI hardware interrupt.
  • Page 820 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCINTENB Description Reset Value 0 = Ignore 1 = Enables interrupt generation due to resume detect. Start of Frame R/WS 0 = Ignore 1 = Enables interrupt generation due to start of frame.
  • Page 821 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 5.2.6 USB HcInterruptDisable Register (UHCINTDISB, R/W, Address = 0xED40_0014) Each disable bit in the UHC Interrupt Disable (UHCINTDISB, shown in Table 8.9-7) register corresponds to an associated interrupt bit in UHCINTSTAT, the UHC Interrupt Status register. The UHC Interrupt Disable register is coupled with the UHC Interrupt Enable register.
  • Page 822 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCINTDIS Description Reset Value 1 = Disables interrupt generation due to HcDoneHead Writeback. Scheduling Overrun 0 = Ignore 1 = Disables interrupt generation due to scheduling overrun. 8.9-22...
  • Page 823 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 5.2.7 USB HcHCCA Register (UHCHCCA, Address = 0xED40_0018) The UHCHCCA register contains the exact physical address of the host controller communication area. Table 8.9-7 UHCHCCA Bit Definitions UHCHCCA Description Reset Value HCCA [31:8] Host Controller Communication Area Base address of the host controller communication area.
  • Page 824 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.9 USB HcControlHeadED Register (UHCHDED, Address = 0xED40_0020) The UHCHDED register contains the physical address of the current Endpoint Descriptor of the control list. The register organization and individual bit definitions are shown in Table 8.9-10. All reserved bits are read as 0 and are unaffected by writes.
  • Page 825 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER Table 8.9-10 UHCCONCURRED Bit Definitions UHCCONCURRE Description Reset Value CCED [31:4] ControlCurrent Enpoint Descriptor This pointer advances to the next ED after serving the present one. The UHC continues processing the list from where it left off in the last frame. If it reaches the...
  • Page 826 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.12 USB HcBulkCurrentED Register (UHCBCURRED, Address = 0xED40_002C) The UHCBCURRED register contains the physical address of the current Endpoint of the Bulk list. The register organization and individual bit definitions are shown in Table 8.9-13. The lower 4 bits are read as 0 and are unaffected by Writes.
  • Page 827 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 5.2.13 USB HcDoneHead Register (UHCDHD, R, Address = 0xED40_0030) The UHCDHD register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. The register organization and individual bit definitions are shown in Table 8.9-14. The lower 4 bits are read as 0 and are unaffected by Writes.
  • Page 828 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Table 8.9-14 UHCFMI Bit Definitions UHCFMI Description Reset Value [31] FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval FSMPS [30:16] FSLargestDataPacket This field specifies a value that is loaded into the Largest Data Packet counter at the beginning of each frame.
  • Page 829 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER Table 8.9-15 UHCFMRM Bit Definitions UHCFMRM Description Reset Value [31] Frame Remaining Toggle Loaded from the Frame Interval Toggle field of the UHC Frame Interval register (UHCFMI[FIT]) whenever the Frame Remaining value (UHCFMR[FR]) reaches 0. This bit is used by the HCD for the synchronization between frame interval and frame remaining.
  • Page 830 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.17 USB HcPeriodicStart Register (UHCPST, R/W, Address = 0xED40_0040) The UHC Periodic Start (UHCPST) register has a 14-bit programmable value that determines the earliest time the UHC must start processing the periodic list.
  • Page 831 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER Table 8.9-18 UHCLSTH Bit Definitions UHCLSTH Description Reset Value Reserved [31:12] Read as unknown and must be written as zero. [11:0] LSThreshold This field contains an 12-bit value that is compared to the Frame Remaining field (UHCFMR[FR]) prior to initiating a low-speed transaction.
  • Page 832 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCRHDA Description Reset Value device. The root hub is not permitted to be a compound device. This field always reads 0. This bit always reads 0. NoPowerSwitching This bit specifies if power-switching is supported or if ports are always powered.
  • Page 833 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER 5.2.20 USB HcRhDescriptorB Register (UHCRHDB, Address = 0xED40_004C) The UHC Root Hub Descriptor B register is the second register of two describing the characteristics of the root hub. These fields are written during initialization to correspond with the system implementation. Only bits 1, 2, 17, and 18 are writable;...
  • Page 834 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.21 USB HcRhStatus Register (UHCRHSTAT, Address = 0xED40_0050) The UHC Root Hub Status register is divided into two parts. The lower word of a word represents the Hub Status field and the upper word represents the Hub Status Change field.
  • Page 835 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCRHSTAT Description Reset Value event. 1 = ConnectStatusChange is a remote wake-up event. Reserved [14:2] Read as unknown and must be written as zero. OverCurrentIndicator This bit reports over-current conditions if the global reporting is implemented.
  • Page 836 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Table 8.9-22 UHCRHPSTAT1 Bit Definitions UHCRHPSTAT Description Reset Value Reserved [31:21] Read as unknown and must be written as zero. PRSC [20] PortResetStatusChange This bit is set at the end of the 10-ms port reset signal.
  • Page 837 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCRHPSTAT Description Reset Value Descriptor B register is set (indicating that this device is not removable), then the CSC bit is set only after a root hub reset to inform the system that the device is attached.
  • Page 838 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCRHPSTAT Description Reset Value reporting is not supported, this bit is forced to 0. If this bit is cleared, all power operations are normal for this port. If set, an over-current condition exists on this port.
  • Page 839 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCRHPSTAT Description Reset Value 0 = Port is disabled. 1 = Port is enabled. (read) CurrentConnectStatus / (write) ClearPortEnable This bit reflects the current state of the downstream port. If a device is connected, this bit reads as 1, and if no device is connected, it is 0.
  • Page 840 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 5.2.23 USB HcRhPortStatus 2 Register (UHCRHPSTAT2, Address = 0xED40_0058) The UHC Root Hub Port Status[2:1] registers control and report USB ports 1 and 2 events on a per-port basis. The lower word of UHCRHPS1/2 reflects the port status, whereas the upper word reflects the status change bits.
  • Page 841 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCRHPSTAT2 Description Reset Value error-babble), cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a 1 to clear this bit. Writing a 0 has no effect 0 = No change in PortEnableStatus.
  • Page 842 USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0) UHCRHPSTAT2 Description Reset Value (read) PortResetStatus / (write) SetPortReset If this bit is set by an HCD write to set port reset, port reset signaling is asserted. If reset is completed, this bit is cleared when PortResetStatusChange is set.
  • Page 843 S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER UHCRHPSTAT2 Description Reset Value This change also causes the port enabled status change bit (UHCRHPS1/2/3[PESC] to be set. The HCD sets the PortEnableStatus bit, by writing a 1 to it, and clears this bit by writing a 1 to clear port enable (UHCRHPS1/2/3[CCS], bit 0 of this register).
  • Page 844 USB2.0 HS OTG 1 OVERVIEW Samsung USB On-The-Go (OTG) is a Dual-Role Device (DRD) controller, which supports both device and host functions. It is fully compliant with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a. It supports high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps, Device only), and low-speed (LS, 1.5-Mbps, Host only) transfers.
  • Page 845 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 3 BLOCK DIAGRAM AHB Slave interface PHY Clock (30 Mhz) USB 2.0 PHY CONTROL Master/Slave Interface USB 2.0 OTG LINK PHY Control Signal PHY Clock (30 Mhz) (clk_sel, etc ) Crystal or Oscillator...
  • Page 846: Modes Of Operation

    S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 4 MODES OF OPERATION The application operates the Link either in DMA mode or in Slave mode. The application cannot operate the core using DMA and Slave modes simultaneously. 4.1 DMA MODE USB OTG host uses the AHB Master interface to transmit packet data fetch (AHB to USB) and receive data update (USB to AHB).
  • Page 847 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 6 MEMORY MAP 6.1 OVERVIEW The OTG PHY control registers based on address ED30_0000h must be accessed to control and observe the OTG PHY. The OTG Link Core registers based on address ED20_0000h is classified as follows: •...
  • Page 848 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 6.3 OTG FIFO ADDRESS MAPPING FIFO FIFO DPTXFSIZ _n [ 31 : 16 ] Periodic - n Tx Packet ( one) DPTXFSIZ _ n[ 15 : 0 ] Periodic Tx Packets HPTXFSIZ [ 31 :16 ]...
  • Page 849 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) Figure 8.10-3 shows the OTG FIFO Address Mapping. The following registers must be programmed as follows; In Host Mode RXFSIZ[15:0] = OTG_RX_DFIFO_DEPTH NPTXFSIZ[15:0] = OTG_RX_DFIFO_DEPTH NPTXFSIZ[31:16] = OTG_TX_NPERIO_DFIFO_DEPTH HPTXFSIZ[15:0] = RX_DFIFO_DEPTH + TX_NPERIO_DFIFO_DEPTH...
  • Page 850 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 6.4 APPLICATION ACCESS TO THE CSRS The Access column of each register description that follows specifies how the application and the core access the register fields of the CSRs. The following conventions are used.
  • Page 851 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 7 I/O DESCRIPTION Function Signal Description Type USB_DP Input/Output Data Plus Signal from the USB Cable Xusb DP Dedicated USB_DM Input/Output Data Minus Signal from the USB Cable XusbDM Dedicated USB_XTI Input Crystal Oscillator XI...
  • Page 852 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8 REGISTER DESCRIPTION 8.1 REGISTER OVERVIEW Table 8.10-1 Register summary of HS OTG Controller Register Offset Description Reset Value OTG PHY CONTROL REGISTERS OPHYPWR 0xED30_0000 R/W OTG PHY Power Control Register 0x0000_0019 OPHYCLK...
  • Page 853 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) Register Offset Description Reset Value DPTXFSIZ13 0xED20_0134 R/W Device Periodic Transmit FIFO-13 Size Register 0x0300_5400 DPTXFSIZ14 0xED20_0138 R/W Device Periodic Transmit FIFO-14 Size Register 0x0300_5700 DPTXFSIZ15 0xED20_013C R/W Device Periodic Transmit FIFO-15 Size Register...
  • Page 854 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG Register Offset Description Reset Value HCINTMSK3 0xED20_056C R/W Host Channel 3 Interrupt Mask Register 0x0000_0000 HCTSIZ3 0xED20_0570 R/W Host Channel 3 Transfer Size Register 0x0000_0000 HCDMA3 0xED20_0574 R/W Host Channel 3 DMA Address Register...
  • Page 855 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) Register Offset Description Reset Value HCINTMSK9 0xED20_062C R/W Host Channel 9 Interrupt Mask Register 0x0000_0000 HCTSIZ9 0xED20_0630 R/W Host Channel 9 Transfer Size Register 0x0000_0000 HCDMA9 0xED20_0634 R/W Host Channel 9 DMA Address Register...
  • Page 856 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG Register Offset Description Reset Value HCINTMSK15 0xED20_06EC R/W Host Channel 15 Interrupt Mask Register 0x0000_0000 HCTSIZ15 0xED20_06F0 R/W Host Channel 15 Transfer Size Register 0x0000_0000 HCDMA15 0xED20_06F4 R/W Host Channel 15 DMA Address Register...
  • Page 857 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) Register Offset Description Reset Value DIEPTSIZ3 0xED20_0970 R/W Device IN Endpoint 3 Transfer Size Register 0x0000_0000 DIEPDMA3 0xED20_0974 R/W Device IN Endpoint 3 DMA Address Register 0x0000_0000 DIEPCTL4 0xED20_0980 R/W Device Control IN Endpoint 0 Control Register...
  • Page 858 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG Register Offset Description Reset Value DIEPTSIZ12 0xED20_0A90 R/W Device IN Endpoint 12 Transfer Size Register 0x0000_0000 DIEPDMA12 0xED20_0A94 R/W Device IN Endpoint 12 DMA Address Register 0x0000_0000 DIEPCTL13 0xED20_0AA0 R/W Device Control IN Endpoint 13 Control Register...
  • Page 859 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) Register Offset Description Reset Value DOEPINT5 0xED20_0BA8 R/W Device OUT Endpoint 5 Interrupt Register 0x0000_0000 DOEPTSIZ5 0xED20_0BB0 R/W Device OUT Endpoint 5 Transfer Size Register 0x0000_0000 DOEPDMA5 0xED20_0BB4 R/W Device OUT Endpoint 5 DMA Address Register...
  • Page 860 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG Register Offset Description Reset Value DOEPINT14 0xED20_0CC8 R/W Device OUT Endpoint 14 Interrupt Register 0x0000_0000 DOEPTSIZ14 0xED20_0CD0 R/W Device OUT Endpoint 14 Transfer Size Register 0x0000_0000 DOEPDMA14 0xED20_0CD4 R/W Device OUT Endpoint 14 DMA Address Register...
  • Page 861 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2 DETAILED DESCRIPTION 8.2.1 OTG PHY Power Control Register (OPHYPWR, R/W, address = 0xED30_0000) OPHYPWR Description Reset Value Reserved [31:5] 27'h0 otg_disable OTG block power down in PHY2.0 1'b1 • 1'b0 : OTG block power up •...
  • Page 862 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.2 OTG PHY Clock Control Register (OPHYCLK, R/W, address = 0xED30_0004) OPHYCLK Description R/W Reset Value Reserved [31:7] - 25'h0 serial_mode UTMI/ Serial Interface Select 1'b0 If this register is asserted, USB traffic flows through the serial interface.
  • Page 863 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) Figure 8.10-4 OTG PHY Clock Path 8.2.3 OTG Reset Control Register (ORSTCON, R/W, address = 0xED30_0008) ORSTCON Description Reset Value Reserved [31:3] 29'h0 phylnk_sw_rst OTG Link Core phy_clock domain S/W Reset 1'b0 link_sw_rst...
  • Page 864 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.4 PHY Tune Register(PHY_TUNE, R/W, address = 0xED30_0020) OPHYTUNE Description Reset Value Reserved [31:21] - 11'h1 [20] HS Transmitter Pre-Emphasis Enable. This signal 1'b0 enables or disables the pre-emphasis for a J-K or K-J state transition in HS mode.
  • Page 865 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) OPHYTUNE Description Reset Value [10:7] FS/ LS Pull-Up Resistance Adjustment. This bit field 4'b0111 adjusts the low-and full-speed pull-up resistance based on nominal power, voltage, and temperature. • 1111 : -2.5% txfslstune • 0111 : Design default •...
  • Page 866 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG These registers are available in both Host and Device modes, and not required to be reprogrammed to switch between these modes. 8.2.5 OTG Control and Status Register (GOTGCTL, R/W, Address = 0xED20_0000) The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.
  • Page 867 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) GOTGCTL Description Reset Value HstNegScs Host Negotiation Success 1'b0 The core sets this bit if host negotiation is successful. The core clears this bit if the HNP Request (HNPReq) bit in this register is set.
  • Page 868 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.6 OTG Interrupt Register (GOTGINT, R/W, Address = 0xED20_0004) The application reads this register at the time of OTG interrupt and clears the bits in this register to clear the OTG interrupt. GOTGINT...
  • Page 869 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.7 OTG AHB Configuration Register (GAHBCFG, R/W, Address = 0xED20_0008) This register configures the core after power-on or a change in mode of operation. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
  • Page 870 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.8 OTG USB Configuration Register (GUSBCFG, R/W, Address = 0xED20_000C) This register configures the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB.
  • Page 871 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.9 Core Reset Register (GRSTCTL, R/W, Address = 0xED20_0010) The application uses this register to reset various hardware features inside the core. GRSTCTL Description Reset Value AHBIdle [31] AHB Master Idle 1'b1 Indicates that the AHB Master State Machine is in the IDLE condition.
  • Page 872 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG GRSTCTL Description Reset Value HSftRst HClk Soft Reset R_WS 1'b0 The application uses this bit to flush the control logic in the AHB Clock domain. Only AHB Clock Domain pipelines are reset. • FIFOs are not flushed with this bit.
  • Page 873 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.10 Core Interrupt Register (GINTSTS, R/W, Address = 0xED20_0014) This register interrupts the application for system-level events in the current mode of operation (Device mode or Host mode). GINTSTS Description Reset Value WkUpInt...
  • Page 874 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG GINTSTS Description Reset Value FetSusp [22] Data Fetch Suspended. This interrupt is valid only in DMA mode. R_SS 1'b0 This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or Request Queue space.
  • Page 875 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) GINTSTS Description Reset Value IEPInt [18] IN Endpoints Interrupt 1'b0 The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The...
  • Page 876 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG GINTSTS Description Reset Value GOUTNak Global OUT NAK Effective 1'b0 Indicates that the Set Global OUT NAK bit in the Device Control register (DCTL.SGOUTNak), set by the application, has taken effect in the core. This bit is cleared by writing the Clear Global OUT NAK bit in the Device Control register.
  • Page 877 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) GINTSTS Description Reset Value CurMod Current Mode Of Operation 1'b0 Indicates the current mode of operation. • 1'b0 : Device mode • 1'b1 : Host mode 8.10 -34...
  • Page 878 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.11 Core Interrupt Mask Register (GINTMSK, R/W, Address = 0xED20_0018) This register works with the Core Interrupt register to interrupt the application. If an interrupt bit is masked, the interrupt associated with that bit will not be generated. However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
  • Page 879 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) GINTMSK Description Reset Value OTGIntMsk OTG Interrupt Mask 1'b0 ModeMisMsk Mode Mismatch Interrupt Mask 1'b0 Reserved 1'b0 8.10 -36...
  • Page 880 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.12 Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP) A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. A read to the Receive Status Read and Pop register additionally pops the top data entry out of the RxFIFO.
  • Page 881 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.14 Device Mode Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP, R, Address = 0xED20_001C, 0xED20_0020) GRXSTSR/ Description Reset Value GRXSTSP Reserved [31:25] 7'h3F [24:21] Frame Number 4'hF This is the least significant 4 bits of the (micro) frame number in which the packet is received on the USB.
  • Page 882 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.15 Receive FIFO Size Register (GRXFSIZ, R/W, Address = 0xED20_0024) The application programs the RAM size that must be allocated to the RxFIFO. GRXFSIZ Description Reset Value Reserved [31:16] 16'h0 RxFDep [15:0] RxFIFO Depth 16'h1800 This value is in terms of 32-bit words.
  • Page 883 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.17 Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS, R, Address = 0xED20_002C) This read-only register contains the free space information for the Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue. GNPTXSTS Description Reset Value...
  • Page 884 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.18 Host Periodic Transmit FIFO Size Register (HPTXFSIZ, R/W, Address = 0xED20_0100) This register holds the size and the memory start address of the Periodic TxFIFO. HPTXFSIZ Description Reset Value PTxFSize [31:16] Host Periodic TxFIFO Depth...
  • Page 885 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.19 Device Periodic Transmit FIFO-n Size Register (DPTXFSIZn, R/W, Address = 0xED20_0104 + (n- 1)*04h) FIFO_number: 1 ≤ n ≤ 15 This register holds the memory start address of each periodic TxFIFO to implement in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
  • Page 886 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG HOST MODE REGISTERS These registers affect the operation of the core in the Host mode. Host mode registers must not be accessed in Device mode, as the results are undefined. Host Mode registers are categorized as follows: •...
  • Page 887 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.21 Host Frame Interval Register (HFIR, R/W, Address = 0xED20_0404) This register stores the frame interval information for the current speed to which the core has enumerated HFNUM Description Reset Value Reserved [31:16] 16’h0...
  • Page 888 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.23 Host Periodic Transmit FIFO/QUEUE Status Register (HPTXSTS, R, Address = 0xED20_0410) This read-only register contains the free space information for the Periodic TxFIFO and the Periodic Transmit Request Queue. HPTXSTS Description Reset Value...
  • Page 889 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.24 Host All Channels Interrupt Register (HAINT, R, Address = 0xED20_0414) If a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register. There is one interrupt bit per channel, up to a maximum of 16 bits.
  • Page 890 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.26 Host Port Control and Status Register (HPRT, R/W, Address = 0xED20_0440) This register is available in both Host and Device modes. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, connect status, and test mode for each port.
  • Page 891 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) HPRT Description Reset Value PrtRst Port Reset 1'b0 If the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete.
  • Page 892 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG HPRT Description Reset Value PrtEnChng Port Enable/Disable Change R_SS_ 1'b0 The core sets this bit if the status of the Port Enable bit [2] of this register changes. PrtEna Port Enable R_SS_ 1'b0...
  • Page 893 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.27 Host Channel-N Characteristics Register (HCCHARn, R/W, Address = 0xED20_0500+n*20h) Channel_number: 0 ≤ n ≤ 15 HCCHARn Description Reset Value ChEna [31] Channel Enable R_WS 1'b0 This field is set by the application and cleared by the OTG host.
  • Page 894 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG HCCHARn Description Reset Value communicating to a low-speed device. Reserved [16] 1'b0 EPDir [15] Endpoint Direction Endpoint Type 1'b0 Indicates the transfer type selected. • 1'b0 : OUT • 1'b1 : IN EPNum...
  • Page 895 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.28 Host Channel-n Split Register (HCSPLTn, R/W, Address = 0xED20_0504+n*20h) Channel_number : 0 ≤ n ≤ 15 HCSPLTn Description Reset Value SpltEna [31] Split Enable 1'b0 The application sets this field to indicate that this channel is enabled to perform split transactions.
  • Page 896 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.29 Host Channel-n interrupt Register (HCINTn, R/W, Address = 0xED20_0508+n*20h) Channel_number : 0 ≤ n ≤ 15 This register indicates the status of a channel with respect to USB- and AHB-related events. The application must read this register if the Host Channels Interrupt bit of the Core Interrupt register is set.
  • Page 897 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.30 Host Channel-n interrupt Mask Register (HCINTMSKn, R/W, Address = 0xED20_050C+n*20h) Channel_number : 0 ≤ n ≤ 15 This register reflects the mask for each channel status described in the previous section. •...
  • Page 898 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.31 Host Channel-n Transfer Size Register (HCTSIZn, R/W, Address = 0xED20_0510+n*20h) Channel_number : 0 ≤ n ≤ 15 HCTSIZn Description Reset Value DoPng [31] Do Ping 1'h0 Setting this field to 1 directs the host to do PING protocol.
  • Page 899 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) DEVICE MODE REGISTERS These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device Mode registers fall into two categories: •...
  • Page 900 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG DCFG Description Reset Value DevSpd [1:0] Device Speed. 2'b0 Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application supports. However the actual bus speed is determined only after the chirp sequence is complete, and is based on the speed of the USB host to which the core is connected.
  • Page 901 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.34 Device Control Register (DCTL, R/W, Address = 0xED20_0804) DCTL Description Reset Value Reserved [31:12] - 20'h0 PWROnPrgDon [11] Power-On Programming Done 1'b0 The application uses this bit to indicate that register programming is complete after a wake-up from Power Down mode.
  • Page 902 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG DCTL Description Reset Value GNPINNakSts Global Non-Periodic IN NAK Status 1'b0 • 1'b0 : A handshake is sent based on the data availability in the transmit FIFO. • 1'b1 : A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
  • Page 903 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.35 Device Status Register (DSTS, R, Address = 0xED20_0808) This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device ALL Interrupts (DAINT) register.
  • Page 904 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.36 Device IN Endpoint Common Interrupt Mask Register (DIEPMSK, R/W, Address = 0xED20_0810) This register works with each of the Device IN Endpoint Interrupt registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register is masked by writing to the corresponding bit in this register.
  • Page 905 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.38 Device ALL Endpoints Interrupt Register (DAINT, R, Address = 0xED20_0818) If a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register.
  • Page 906 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.40 Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1, R, Address = 0xED20_0820) The queue is 4 bits wide to store the endpoint number. A read from this register returns the first 5 endpoint entries of the IN Token Sequence Learning Queue.
  • Page 907 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.42 Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3, R, Address = 0xED20_0830) Read from this register returns the next 8 endpoint entries of the learning queue. DTKNQR3 Description Reset Value...
  • Page 908 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.45 Device VBUS Pulsing Time Register (DVBUSPULSE, R/W, Address = 0xED20_082C) This register specifies the VBUS discharge time during SRP. DVBUSPULSE Description Reset Value Reserved [31:12] - 16'h0 DVBUSPulse [11:0] Device VBUS Pulsing Time 12'h5B8 Specifies the VBUS pulsing time during SRP.
  • Page 909 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.46 Device Logical Endpoint-Specific Registers A logical endpoint is unidirectional: it is either IN or OUT. To represent a bidirectional endpoint, two logical endpoints are required, one for the IN direction and the other for the OUT direction. This is also true for control endpoints.
  • Page 910 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG DIEPCTL0 Description Reset Value NAKsts [17] NAK Status 1'b0 Indicates the following: • 1'b0 : The core is transmitting non-NAK handshakes based on the FIFO status • 1'b1 : The core is transmitting NAK handshakes on this...
  • Page 911 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.48 Device Control OUT Endpoint 0 Control Register (DOEPCTL0, R/W, Address =0xED20_0B00) This section describes the Control OUT Endpoint 0 Control register. Nonzero control endpoints use registers for endpoints 1-15. DOEPCTL0 Description Reset...
  • Page 912 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG DOEPCTL0 Description Reset Value NAKsts [17] NAK Status 1'b0 Indicates the following: • 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status • 1'b1: The core is transmitting NAK handshakes on this...
  • Page 913 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.49 Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn, R/W, Address = 0xED20_0900+ n*20h, 0xED20_0B00+ n*20h) Endpoint_number :1 ≤ n ≤ 15 The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  • Page 914 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG DIEPCTLn/ Description Reset DOEPCTLn Value a Transfer Complete interrupt, or after a SETUP packet is received on that endpoint. CNAK [26] Clear NAK 1'b0 Applies to IN and OUT endpoints. A write to this bit clears the NAK bit for the endpoint.
  • Page 915 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) DIEPCTLn/ Description Reset DOEPCTLn Value • The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. • For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
  • Page 916 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.50 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn, R/W, Address = 0xED20_0908 +n*20h, 0xED20_0B08 +n*20h) Endpoint_number : 0 ≤ n ≤ 15 This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register if the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register is set.
  • Page 917 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) DIEPINTn/ Description Reset Value DOEPINTn SetUp SETUP Phase Done Applies to control OUT endpoints only. Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer.
  • Page 918 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.51 Device Endpoint 0 Transfer Size Register (DIEPTSIZ0, R/W, Address = 0xED20_0910) The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers, the core modifies this register. The application reads this register after the core has cleared the Endpoint Enable bit.
  • Page 919 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) 8.2.52 Device OUT Endpoint 0 Transfer Size Register (DOEPTSIZ0, R/W, Address = 0xED20_0B10) DOEPTSIZ0 Description Reset Value Reserved [31] 1'b0 SUPCnt [30:29] SETUP Packet Count 2'h0 This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
  • Page 920 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.53 Device Endpoint-N Transfer Size Register (DIEPTSIZn/DOEPTSIZn, R/W, Address = 0xED20_0910 +n*20h, 0xED20_0B10 +n*20h) Endpoint_number: 1 ≤ n ≤ 15 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint Enable bit of the Device Endpoint-n Control registers, the core modifies this register.
  • Page 921 USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0) XferSize [18:0] 19'h0 Transfer Size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size is set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.
  • Page 922 S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG 8.2.55 Power and Clock Gating control register (PCGCCTL, R/W, Address = 0xED20_0E00) The application uses this register to control OTG's clock gating. DIEPTSIZ0 Description Reset Value Reserved [31:1] 31'h0 StopPclk STOP Pclk 1'b0...
  • Page 923 This specification defines the interface between the Base-band Modem (like MSM) and the Application Processor for the data-exchange of these two devices (Refer Figure 8.11-1). For the data-exchange, the AP (Application Processor, S5PC100) has a dual-ported SRAM buffer (on-chip). The Modem chip accesses SRAM buffer using a typical asynchronous-SRAM interface.
  • Page 924 MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0) 2 FEATURES • Asynchronous SRAM interface style interface • Supports both Standard mode and Address Muxed mode • Supports 16-bit parallel bus for data transfer • Supports 16 KB internal dual-port SRAM buffer •...
  • Page 925 There are two address views for MODEMIF, one is MSM address (ADR) for MODEM chip, and the other one is AHB address for S5PC100. AHB address is twice of ADR. For example, 0x3FFC at AHB bus is 0x1FFE at ADR.
  • Page 926: Address Mapping

    MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0) 4 ADDRESS MAPPING Figure 8.11-2 MODEM I/F Address Mapping 8.11-4...
  • Page 927 S5PC100 USER’S MANUAL (REV1.0) MODEM INTERFACE 5 TIMING DIAGRAM 5.1 STANDARD MODE WRITE, READ TIMING AVWR CSVWR DSUWR DHWR DATA Figure 8.11-3 Modem Interface Write Timing Diagram (Standard Mode) Table 8.11-2 Modem Interface Write Timing (Standard mode) Parameter Description Min (ns)
  • Page 928 MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0) AVRD CSVRD CSRD RDDV DATA ACSDV Figure 8.11-4 Modem Interface Read Timing Diagram (Standard Mode) Table 8.11-3 Modem interface read timing (Standard Mode) Parameter Description Min (ns) Max (ns) Notes Address Valid to Address Invalid...
  • Page 929 S5PC100 USER’S MANUAL (REV1.0) MODEM INTERFACE 5.2 ADDRESS MUXED MODE WRITE, READ TIMING Figure 8.11-5 Modem Interface Write Timing Diagram (Address Muxed Mode) Table 8.11-4 Modem Interface Write Timing (Address Muxed Mode) Parameter Description Min (ns) Max (ns) Notes Address Valid Setup...
  • Page 930 MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0) Figure 8.11-6 Modem Interface Read Timing Diagram (Address Muxed Mode) Table 8.11-5 Modem interface read timing (Address Muxed Mode) Parameter Description Min (ns) Max (ns) Notes Address Valid Setup 15 ns AVDS Address Valid Hold...
  • Page 931 S5PC100 USER’S MANUAL (REV1.0) MODEM INTERFACE 6 I/O DESCRIPTION Function Description Type Signal MSM_A[12:0] Input Address from MODEM Chip XmsmADDR[12:0] muxed MSM_CSn Input Chip Select Signal from MODEM Chip XmsmCSn muxed MSM_WEn Input Write Enable Signal from MODEM Chip XmsmWEn...
  • Page 932 MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0) 8 REGISTER DESCRIPTION Register Address Description Reset Value 0xED50_0000 ~ MSBM MODEM I/F SRAM Buffer Memory (AP side) 0xED50_3FFC Register Address Description Reset Value INT2AP 0xED50_8000 Interrupt Request to AP Register 0x00003FFE INT2MSM 0xED50_8004...
  • Page 933 S5PC100 USER’S MANUAL (REV1.0) MODEM INTERFACE 8.3 MODEM INTERFACE CONTROL REGISTER (MIFCON, R/W, ADDRESS = 0XED50_8008) MIFCON Description Reset Value Reserved [31:21] Reserved Fixed [20] Shoud write as 1 DMARXREQEN_1 [19] Enables MSM Write DMA Request (RX 1) to AP (DMA Controller)
  • Page 934 [31:0] Write access to this register with any data will clear the interrupt pending register of MSM modem interface. NOTE: The interrupt controllers of AP (S5PC100) receive level-triggered type interrupt requests. Therefore, interrupt requests from MSM interface are maintained until the interrupt service routine clears the interrupt pending register by writing any data into this register.
  • Page 935 S5PC100 USER’S MANUAL (REV1.0) MODEM INTERFACE NOTES 8.11-13...
  • Page 936 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 8.12 SD/MMC CONTROLLER This chapter describes the Secure Digital (SD/ SDIO), MultiMediaCard (MMC), CE-ATA host controller and related registers supported by S5PC100X RISC microprocessor. 1 OVERVIEW The SD/ MMC host controller is a combo host for Secure Digital card and MultiMediaCard. This host is based on SD Association’s (SDA) Host Standard Specification.
  • Page 937 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 3 BLOCK DIAGRAM HCLK SDCLK Domain Domain BaseCLK Status Clock Control INTREQ Status CMDRSP System packet (AHB) Line Control Control Control FIFO AHB slave I/F Control Control DPSRAM Status controller DATA AHB master packet Figure 8.12-1 HSMMC Block Diagram...
  • Page 938 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 4 SEQUENCE This section defines basic sequence flow chart divided into several sub sequences. "Wait for interrupts" is used in the flow chart. This means the Host Driver waits until specified interrupts are asserted. If already asserted, then follow the next step in the flow chart.
  • Page 939 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.2 SD CLOCK SUPPLY SEQUENCE Figure 8.12-3 SD Clock Supply Sequence The sequence to set SD Clock to a SD card is described in Figure 8.12-3. The clock is enabled before one of the following actions is taken.
  • Page 940 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 4.3 SD CLOCK STOP SEQUENCE Figure 8.12-4 SD Clock Stop Sequence The flow chart for stopping the SD Clock is shown in Figure 8.12-4. The Host Driver does not stop the SD Clock if a SD transaction takes place on the SD Bus -- namely, when either Command Inhibit (DAT) or Command Inhibit (CMD) in the Present State register is set to 1.
  • Page 941 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.5 SD BUS POWER CONTROL SEQUENCE START Get the support voltage of the Host Controller Set SD Bus voltage select with supported maximum voltage Set SD Bus Power Get OCR value of the SD Card...
  • Page 942 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 4.6 CHANGE BUS WIDTH SEQUENCE Figure 8.12-7 Change Bus Width Sequence The sequence to change bit mode on SD Bus is shown in Figure 8.12-7 and steps are described below: (1) Set Card Interrupt Status Enable (STACARDINT) in the Normal Interrupt Status Enable register to 0 to mask incorrect interrupts that may occur while changing the bus width.
  • Page 943 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.7 TIMEOUT SETTING FOR DAT LINE START Calculate a Divisor for detecting Timeout Set Timeout Detection Timer Figure 8.12-8 Timeout Setting Sequence In order to detect timeout errors on DAT line, the Host Driver executes the following two steps before any SD transaction.
  • Page 944 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 4.9 SD COMMAND ISSUE SEQUENCE Figure 8.12-9 Timeout Setting Sequence 8.12-9...
  • Page 945 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Take the following steps to set Timeout: (1) Check Command Inhibit (CMD) in the Present State register. Repeat this step until Command Inhibit (CMD) is 0. If Command Inhibit (CMD) is 1, the Host Driver does not issue a SD Command.
  • Page 946 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER START Wait for Command Complete Int Command Complete Int occur Clear Command Complete Status Get Response Data Command with Transfer Complete Int ? Wait for Transfer Complete Int Transfer Complete Int occur Clear Transfer Complete Status...
  • Page 947 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 4.11 TRANSACTION CONTROL WITH DATA TRANSFER USING DAT LINE Depending on whether DMA (optional) is used or not, there are two execution methods. The sequence without using DMA is shown in Figure 8.12-11 and the sequence using DMA is shown in Figure 8.12-12.
  • Page 948 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 4.12 NOT USING DMA Figure 8.12-11 Transaction Control with Data Transfer Using DAT Line Sequence (Not using DMA) 8.12-13...
  • Page 949 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) (1) Set the value corresponding to the executed data byte length of one block to Block Size register. (2) Set the value corresponding to the executed data block count to Block Count register. (3) Set the value corresponding to the issued command to Argument register.
  • Page 950 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 4.13 USING DMA Figure 8.12-12 Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA) (1) Set the system address for DMA in the System Address register. (2) Set the value corresponding to the executed data byte length of one block in the Block Size register.
  • Page 951 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) (7) Wait for the Command Complete Interrupt. (8) Write 1 to the Command Complete (STACMDCMPLT) in the Normal Interrupt Status register to clear this bit. (9) Read Response register and get necessary information in accordance with the issued command.
  • Page 952 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 7 ADMA(ADVANCED DMA) In the SD Host Controller Standard Specification Version 2.00, new DMA transfer algorithm called ADMA (Advanced DMA) is defined. The DMA algorithm defined in the SD Host Controller Standard Specification Version 1.00 is called SDMA (Single Operation DMA).
  • Page 953 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.2 AN EXAMPLE OF ADMA PROGRAMMING Figure 8.12- 14 An Example of ADMA Data Transfer Figure 8.12-14 shows a typical ADMA descriptor program. The data area is sliced in various lengths and each slice is placed somewhere in system memory. The Host Driver describes the Descriptor Table with set of address, length and attributes.
  • Page 954 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 7.4 DESCRIPTOR TABLE Figure 8.12- 15 32-bit Address Descriptor Table Figure 8.12-15 shows the definition of 32-bit Address Descriptor Table. One descriptor line consumes 64-bit (8- byte) memory space. Attribute is used to control descriptor. 3 action symbols are specified. "Nop" operation skips current descriptor line and fetches next one.
  • Page 955 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 7.5 ADMA STATES Figure 8.12-16 shows state diagram of ADMA. 4 states are defined; Fetch Descriptor state, Change Address state, Transfer Data state, and Stop ADMA state. Operation of each state is explained in Table 8.12-3.
  • Page 956 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER Read Wait or stopping SD Clock. While stopping ADMA, any SD commands cannot be issued. (In case of Host Controller version 1.00, the Stop At Block Gap Request can be set only when the card supports the Read Wait.) Error occurrence during ADMA transfer may stops ADMA operation and generates ADMA Error Interrupt.
  • Page 957 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Function Signal Descrioption Type SD_1_D[3] IN/OUT Data for HSMMC1 Xmmc1DATA[3] muxed SD_1_CDn INPUT Card Detect for HSMMC1 Xmmc1CDn muxed SD_2_CLK OUTPUT Clock for HSMMC2 Xmmc2CLK muxed SD_2_CMD IN/OUT Command for HSMMC2 Xmmc2CMD muxed SD_2_D[0]...
  • Page 958 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER Register Address Description Reset Value NORINTSTS0 0xED80_0030 ROC/ Normal Interrupt Status Register (Channel RW1C ERRINTSTS0 0xED80_0032 ROC/ Error Interrupt Status Register (Channel 0) RW1C NORINTSTSEN0 0xED80_0034 Normal Interrupt Status Enable Register (Channel 0) ERRINTSTSEN0...
  • Page 959 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value BDATA1 0xED90_0020 Buffer Data Register (Channel 1) PRNSTS1 0xED90_0024 R/ROC Present State Register (Channel 1) 0x000A0000 HOSTCTL1 0xED90_0028 Host Control Register (Channel 1) PWRCON1 0xED90_0029 Power Control Register (Channel 1)
  • Page 960 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER Register Address Description Reset Value BLKSIZE2 0xEDA0_0004 Host DMA Buffer Boundary and Transfer Block Size Register (Channel 2) BLKCNT2 0xEDA0_0006 Blocks count for current transfer (channel 2) ARGUMENT2 0xEDA0_0008 Command Argument Register (Channel 2)
  • Page 961 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Register Address Description Reset Value Register (Channel 2) FEERR2 0xEDA0_0052 Force Event Error Interrupt Register Error 0x0000 Interrupt (Channel 2) ADMAERR2 0xEDA0_0054 ADMA Error Status Register (Channel 2) 0x00 ADMASYSADDR2 0xEDA0_0058 ADMA System Address Register (Channel...
  • Page 962 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.2 BLOCK SIZE REGISTER Host DMA Buffer Boundary and Transfer Block Size Register • BLKSIZE0, R/W, Address = 0xED80_0004 • BLKSIZE1, R/W, Address = 0xED90_0004 • BLKSIZE2, R/W, Address = 0xEDA0_0004 This register is used to configure the number of bytes in a data block.
  • Page 963 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) BLKSIZE [11:0] Transfer Block Size This register specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to maximum buffer size are set. In case of memory, it is set up to 512 bytes.
  • Page 964 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.3 BLOCK COUNT REGISTER Blocks Count for Current Transfer • BLKCNT0, R/W, Address = 0xED80_0006 • BLKCNT1, R/W, Address = 0xED90_0006 • BLKCNT2, R/W, Address = 0xEDA0_0006 This register is used to configure the number of data blocks.
  • Page 965 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.4 ARGUMENT REGISTER Command Argument Register • ARGUMENT0, R/W, Address = 0xED80_0008 • ARGUMENT1, R/W, Address = 0xED90_0008 • ARGUMENT2, R/W, Address = 0xEDA0_0008 This register contains the SD Command Argument. ARGUMENT Description Reset Value...
  • Page 966 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER TRNMOD Description Reset Value RD1WT0 Data Transfer Direction Select This bit defines the direction of DAT line data transfers. The bit is set to 1 by the Host Driver to transfer data from the SD card to the SD Host Controller and it is set to 0 for all other commands.
  • Page 967 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.6 COMMAND REGISTER Command Register • CMDREG0, R/W, Address = 0xED80_000E • CMDREG1, R/W, Address = 0xED90_000E • CMDREG2, R/W, Address = 0xEDA0_000E This register contains the SD Command Argument. The Host Driver checks the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State register before writing to this register.
  • Page 968 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER CMDREG Description Reset Value DATAPRNT Data Present Select This bit is set to 1 to indicate that data is present and transferred using the DAT line. It is set to 0 for the following: (1) Commands using only CMD line (ex.
  • Page 969 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.7 RESPONSE REGISTER This register is used to store responses from SD cards. • Response Register 0 (Channel 0) (RSPREG0_0, ROC, Address = 0xED80_0010) • Response Register 1 (Channel 0) (RSPREG1_0, ROC, Address = 0xED80_0014) •...
  • Page 970 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER Response Bit Definition for Each Response Type. Kind of Response Meaning of Response Response Field Response Register R1, R1b (normal response) Card Status R [39:8] REP [31:0] R1b (Auto CMD12 response) Card Status for Auto CMD12...
  • Page 971 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.9 PRESENT STATE REGISTER Present State Register • PRNSTS0, R/ROC, Address = 0xED80_0024 • PRNSTS1, R/ROC, Address = 0xED90_0024 • PRNSTS2, R/ROC, Address = 0xEDA0_0024 This register contains the SD Command Argument. PRNSTS Description...
  • Page 972 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER PRNSTS Description Reset Value Software Reset register does not affect this bit. If a card is removed while its power is on and its clock is oscillating, the Host Controller clears SD Bus Power in the Power Control register and SD Clock Enable in the Clock Control register.
  • Page 973 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) PRNSTS Description Reset Value WTTRANACT Write Transfer Active (ROC) This status indicates that a write transfer is active. If this bit is 0, it means no valid write data exists in the Host Controller.
  • Page 974 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER PRNSTS Description Reset Value This bit is set in either of the following cases: (1) After the end bit of the write command. (2) If 1 is written to Continue Request in the Block Gap Control register to continue a write transfer.
  • Page 975 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) Stable SDCD#=1 Card Inserted Power ON Reset Debouncing Once debouncing clock becomes valid Stable No Card SDCD#=0 Figure 8.12-17 Card Detect State The above Figure 8.12-17 shows the state definitions of hardware that handles "Debouncing".
  • Page 976 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER Figure 8.12-18 Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with Data Transfer Figure 8.12-19 Timing of Command Inhibit (DAT) for the Case of Response with Busy Figure 8.12-20 Timing of Command Inhibit (CMD) for the Case of No Response Command...
  • Page 977 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.10 HOST CONTROL REGISTER Host Control Register • HOSTCTL0, R/W, Address = 0xED80_0028 • HOSTCTL1, R/W, Address = 0xED90_0028 • HOSTCTL2, R/W, Address = 0xEDA0_0028 This register contains the SD Command Argument. HOSTCTL Description...
  • Page 978 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.11 POWER CONTROL REGISTER Power Control Register • PWRCON0, R/W, Address = 0xED80_0029 • PWRCON1, R/W, Address = 0xED90_0029 • PWRCON2, R/W, Address = 0xEDA0_0029 This register contains the SD Command Argument. PWRCON Description...
  • Page 979 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.12 BLOCK GAP CONTROL REGISTER Block Gap Control Register • BLKGAP0, R/W, 0xED80_002A • BLKGAP1, R/W, 0xED90_002A • BLKGAP2, R/W, 0xEDA0_002A This register contains the SD Command Argument. BLKGAP Description Reset Value Reserved [7:4] Reserved...
  • Page 980 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER BLKGAP Description Reset Value DMA and non-DMA transfers. Until the Transfer Complete is set to 1, indicating a transfer completion the Host Driver leaves this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request does not restart the transaction.
  • Page 981 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.13 WAKEUP CONTROL REGISTER Wakeup Control Register • WAKCON0, R/W, Address = 0xED80_002B • WAKCON1, R/W, Address = 0xED90_002B • WAKCON2, R/W, Address = 0xEDA0_002B This register is mandatory for the Host Controller, but wakeup functionality depends on the Host Controller system hardware and software.
  • Page 982 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.14 CLOCK CONTROL REGISTER Clock Control Register • CLKCON0, R/W, Address = 0xED80_002C • CLKCON1, R/W, Address = 0xED90_002C • CLKCON2, R/W, Address = 0xEDA0_002C At the initialization of the Host Controller, the Host Driver sets the SDCLK Frequency Select according to the Capabilities register.
  • Page 983 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) CLKCON Description Reset Value Reserved [7:4] Reserved External Clock Stable STBLEXTCLK This bit is set to 1 if SD Clock output is stable after writing to SD Clock Enable in this register to 1. The SD Host Driver waits to issue command to start until this bit is set to 1.
  • Page 984 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.15 TIMEOUT CONTROL REGISTER Timeout Control Register • TIMEOUTCON0, R/W, Address = 0xED80_002E • TIMEOUTCON1, R/W, Address = 0xED90_002E • TIMEOUTCON2, R/W, Address = 0xEDA0_002E At the initialization of the Host Controller, the Host Driver sets the Data Timeout Counter Value according to the Capabilities register.
  • Page 985 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.16 SOFTWARE RESET REGISTER Software Reset Register • SWRST0, R/W, Address = 0xED80_002F • SWRST1, R/W, Address = 0xED90_002F • SWRST2, R/W, Address = 0xEDA0_002F A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the Host Controller clears each bit.
  • Page 986 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER SWRST Description Reset Value to 0. During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. The Host Controller reset this bit to 0 if capabilities registers are valid and the Host Driver reads them. If this bit is set to 1, the SD card resets itself and must be reinitialized by the Host Driver.
  • Page 987 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.17 NORMAL INTERRUPT STATUS REGISTER Normal Interrupt Status Register • NORINTSTS0, ROC/RW1C, Address = 0xED80_0030 • NORINTSTS1, ROC/RW1C, Address = 0xED90_0030 • NORINTSTS2, ROC/RW1C, Address = 0xEDA0_0030 The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not affect these reads.
  • Page 988 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER NORINTSTS Description Reset Value Read Wait interrupt status manually if BS = 0 (BS means 'Bus Status' field 'Bus Suspend' register in the SDIO card specification) Note: Read Wait operation procedure is started after 4-SDCLK from the end of the block data read transfer.
  • Page 989 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) NORINTSTS Description Reset Value STABUFRDRD Buffer Read Ready This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the Buffer Read Enable in the Present State register. (RW1C)
  • Page 990 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER NORINTSTS Description Reset Value data is written to the SD card as specified by data length and the busy signal released. The second if data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control register and data transfers complete.
  • Page 991 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.18 ERROR INTERRUPT STATUS REGISTER Error Interrupt Status Register • ERRINTSTS0, ROC/RW1C, Address = 0xED80_0032 • ERRINTSTS1, ROC/RW1C, Address = 0xED90_0032 • ERRINTSTS2, ROC/RW1C, Address = 0xEDA0_0032 Signals defined in this register are enabled by the Error Interrupt Status Enable register, but not by the Error Interrupt Signal Enable register.
  • Page 992 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER ERRINTSTS Description Reset Value Occurs if it detects one of following timeout conditions. (1) Busy timeout for R1b, R5b type (2) Busy timeout after Write CRC status (3) Write CRC Status timeout (4) Read Data timeout.
  • Page 993 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) The relation between Command CRC Error and Command Timeout Error is shown in Table below. The relation between Command CRC Error and Command Timeout Error Command CRC Error Command Timeout Error Kinds of error...
  • Page 994 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.19 NORMAL INTERRUPT STATUS ENABLE REGISTER Normal Interrupt Status Enable Register • NORINTSTSEN0, R/W, Address = 0xED80_0034 • NORINTSTSEN1, R/W, Address = 0xED90_0034 • NORINTSTSEN2, R/W, Address = 0xEDA0_0034 Setting to 1 enables Interrupt Status.
  • Page 995 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) NORINTSTSEN Description Reset Value Card Insertion Status Enable ENSTACARDNS '1' = Enabled '0' = Masked Buffer Read Ready Status Enable ENSTABUFRDRDY '1' = Enabled '0' = Masked Buffer Write Ready Status Enable ENSTABUFWTRDY '1' = Enabled...
  • Page 996 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.20 ERROR INTERRUPT STATUS ENABLE REGISTER Error Interrupt Status Enable Register • ERRINTSTSEN0, R/W, 0xED80_0036 • ERRINTSTSEN1, R/W, 0xED90_0036 • ERRINTSTSEN2, R/W, 0xEDA0_0036 Setting to 1 enables Error Interrupt Status. ERRINTSTSEN Description Reset Value...
  • Page 997 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.21 NORMAL INTERRUPT SIGNAL ENABLE REGISTER Normal Interrupt Signal Enable Register • NORINTSIGEN0, R/W, Address = 0xED80_0038 • NORINTSIGEN1, R/W, Address = 0xED90_0038 • NORINTSIGEN2, R/W, Address = 0xEDA0_0038 This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status bits share the same1 bit interrupt line.
  • Page 998 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER NORINTSIGEN Description Reset Value ENSIGBUFRDRDY Buffer Read Ready Signal Enable '1' = Enabled '0' = Masked ENSIGBUFWTRDY Buffer Write Ready Signal Enable '1' = Enabled '0' = Masked ENSIGDMA DMA Interrupt Signal Enable '1' = Enabled...
  • Page 999 SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0) 9.22 ERROR INTERRUPT SIGNAL ENABLE REGISTER Error Interrupt Signal Enable Register • ERRINTSIGEN0, R/W, Address = 0xED80_003A • ERRINTSIGEN1, R/W, Address = 0xED90_003A • ERRINTSIGEN2, R/W, Address = 0xEDA0_003A This register is used to select which interrupt status is notified to the Host System as the interrupt. These status bits share the same 1 bit interrupt line.
  • Page 1000 S5PC100 USER’S MANUAL (REV1.0) SD/MMC CONTROLLER 9.23 AUTOCMD12 ERROR STATUS REGISTER Auto CMD12 Error Status Register • ACMD12ERRSTS0, ROC, Address = 0xED80_003C • ACMD12ERRSTS1, ROC, Address = 0xED90_003C • ACMD12ERRSTS2, ROC, Address = 0xEDA0_003C If Auto CMD12 Error Status is set, the Host Driver checks this register to identify what kind of error Auto CMD12 indicated.

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