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Samsung KS57C2308 Manual

Single-chip cmos microcontroller.
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KS57C2308/P2308/C2316/P2316

PRODUCT OVERVIEW

1
PRODUCT OVERVIEW
OVERVIEW
The KS57C2308/C2316 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the KS57C2308/C2316 offer
an excellent design solution for a wide variety of applications that require LCD functions.
Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response
to internal and external events. In addition, the KS57C2308/C2316's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The KS57C2308/C2316 microcontroller is also available in OTP (One Time Programmable) version,
KS57P2308/P2316. KS57P2308/P2316 microcontroller has an on-chip 8/16-Kbyte one-time-programmable
EPROM instead of masked ROM. The KS57P2308/P2316 is comparable to KS57C2308/C2316, both in function
and in pin configuration.
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   Summary of Contents for Samsung KS57C2308

  • Page 1: Product Overview

    The KS57C2308/C2316 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the KS57C2308/C2316 offer an excellent design solution for a wide variety of applications that require LCD functions.

  • Page 2

    PRODUCT OVERVIEW FEATURES Memory – 4-bit RAM – 8-bit ROM (KS57C2308/P2308) – 16 K 8-bit ROM (KS57C2316/P2316) I/O Pins – Input only: 8 pins – I/O: 24 pins – Output: 8 pins sharing with segment driver outputs LCD Controller/Driver –...

  • Page 3: Block Diagram

    P5.0-P5.3 I/O Port 4 P6.0-P6.3/ I/O Port 6 KS0-KS3 P7.0-P7.3/ I/O Port 7 KS4-KS7 P8.0-P8.7/ I/O Port 8 SEG24-SEG31 Figure 1-1. KS57C2308/C2316 Simplified Block Diagram Watch-Dog Basic Timer Timer X IN X OUT RESET XT IN XT OUT Instruction Interrupt...

  • Page 4: Table Of Contents

    V DD V SS X OUT X IN TEST XT IN XT OUT RESET P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI P1.0/INT0 Figure 1-2. KS57C2308/C2316 80-QFP Pin Assignment Diagram KS57C2308 KS57C2316 (TOP VIEW) KS57C2308/P2308/C2316/P2316 SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28...

  • Page 5: Pin Descriptions

    –V – LCD power supply. Voltage dividing resistors are assignable by mask option BIAS – LCD power control LCDCK LCD clock output for display expansion Table 1-1. KS57C2308/C2316 Pin Descriptions Description PRODUCT OVERVIEW Number Share Reset Value INT4 Input INT0...

  • Page 6

    PRODUCT OVERVIEW Table 1-1. KS57C2308/C2316 Pin Descriptions (Continued) Pin Name Type LCDSY LCD synchronization clock output for LCD display expansion TCL0 External clock input for timer/counter 0 TCLO0 Timer/counter 0 clock output Serial interface data input Serial interface data output...

  • Page 7

    KS57C2308/P2308/C2316/P2316 PIN CIRCUIT DIAGRAMS Figure 1-3. Pin Circuit Type A PULL-UP RESISTOR P-CHANNEL SCHMITT TRIGGER Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3) P-CHANNEL N-CHNNEL RESISTOR ENABLE PRODUCT OVERVIEW DATA OUTPUT DISABLE Figure 1-5. Pin Circuit Type C RESISTOR...

  • Page 8: Seg2

    Figure 1-7. Pin Circuit Type E (P4, P5) LCD SEGMENT/ COMMON DATA Figure 1-8. Pin Circuit Type H-15 (SEG/COM) PULL-UP RESISTOR RESISTOR ENABLE KS57C2308/P2308/C2316/P2316 LCD SEGMENT/ & PORT 8 DATA Figure 1-9. Pin Circuit Type H-16 (P8) SCHMITT TRIGGER Figure 1-10. Pin Circuit Type B ( RESET...

  • Page 9: Address Spaces

    PROGRAM MEMORY (ROM) OVERVIEW ROM maps for KS57C2 308/C2316 devices are mask programmable at the factory. KS57C2308 has 8K program memory and KS57C2316 has 16K the two products are identical in other features. In its standard configuration, the device's 8,192 8-bit) program memory has four areas that are directly addressable by the program counter (PC): —...

  • Page 10

    REFERENCE AREA 007FH 0080H GENERAL-PURPOSE AREA (8,064 Bytes/ 16,256 Bytes) 1FFFH 3FFFH Figure 2-1. ROM Address Structure (note) PC12 PC11 PC13 KS57C2308/P2308/C2316/P2316 PC10 0000H RESET 0002H INTB/INT4 0004H INT0 0006H INT1 0008H INTS 000AH INTT0 Figure 2-2. Vector Address Structure...

  • Page 11

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — Defining Vectored Interrupts The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: 0000H VENT0 1,0,RESET VENT1 0,0,INTB VENT2...

  • Page 12

    • KEYCK JMAIN WATCH INCHL • • • KS57C2308/P2308/C2316/P2316 ; 0, MAIN ; 1, KEYFG CHECK ; 2, CALL CLOCK ; 3, (HL) ; 47, EA #00H ; BTSF KEYFG (1-byte instruction) ; KEYFG = 1, jump to MAIN (1-byte instruction) ;...

  • Page 13

    KS57C2308/P2308/C2316/P2316 DATA MEMORY (RAM) OVERVIEW In its standard configuration, the 512 x 4-bit data memory has four areas: — 32 4-bit working register area in bank 0 — 224 4-bit general-purpose area in bank 0 which is also used as the stack area —...

  • Page 14

    The lowest 224 nibbles of bank1 (100H–1DFH) are for general–purpose use; Use the remaining of 32 nibbles (1E0H–1FFH) as display registers or as general purpose memory. The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed RAM locations for each peripheral hardware address are mapped into this area. KS57C2308/P2308/C2316/P2316...

  • Page 15

    KS57C2308/P2308/C2316/P2316 Table 2-2. Data Memory Organization and Addressing Addresses 000H–01FH Working registers 020H–0FFH Stack and general-purpose registers 100H–1DFH General-purpose registers 1E0H–1FFH LCD Data registers F80H–FFFH I/O-mapped hardware registers PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1 Clear banks 0 and 1 of the data memory area:...

  • Page 16

    8-bit units. 000H 001H 002H 003H 004H 005H DATA 006H MEMORY BANK 0 007H 008H 00FH 010H 017H 018H 01FH Figure 2-4. Working Register Map KS57C2308/P2308/C2316/P2316 WORKING REGISTER BANK 0 REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3...

  • Page 17

    KS57C2308/P2308/C2316/P2316 Working Register Banks For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRB n) and by setting the status of the register bank enable flag (ERB).

  • Page 18

    When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction. 2-10 Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator KS57C2308/P2308/C2316/P2316 1-BIT ACCUMULATOR 4-BIT ACCUMULATOR...

  • Page 19

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — Selecting the Working Register Area The following examples show the correct programming method for selecting working register area: 1. When ERB = "0": VENT2 1,0,INT0 INT0 PUSH PUSH PUSH PUSH PUSH EA,#00H 80H,EA HL,#40H INCS WX,EA...

  • Page 20: Stack Operations

    2. When EMB = "0": EA,#00H SP,EA 2-12 "0" NOTE ; Select memory bank 15 ; Bit 0 of SP is always cleared to "0" ; Stack area initial address (0FFH) ; Memory addressing area (00H–7FH, F80H–FFFH) KS57C2308/P2308/C2316/P2316 (SP) – 1...

  • Page 21

    KS57C2308/P2308/C2316/P2316 PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decreased by a number determined by the type of push operation and then points to the next available stack location.

  • Page 22

    SP + 3 PC7 – PC4 SP + 4 EMB ERB SP + 5 SP + 6 Figure 2-8. Pop-Type Stack Operations KS57C2308/P2308/C2316/P2316 IRET SP + 6) PC11 – PC8 SP + 1 PC13 PC12 SP + 2 PC3 – PC0 SP + 3 PC7 –...

  • Page 23

    KS57C2308/P2308/C2316/P2316 BIT SEQUENTIAL CARRIER (BSC) The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM control instructions. clears all BSC bit values to logic zero. RESET Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L).

  • Page 24

    Table 2-5. Program Status Word Bit Descriptions PSW Bit Identifier IS1, IS0 Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag SC2, SC1, SC0 Program skip flags 2-16 (LSB) Description KS57C2308/P2308/C2316/P2316 vector address, and the RESET Bit Addressing Read/Write 1, 4...

  • Page 25

    KS57C2308/P2308/C2316/P2316 INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence.

  • Page 26

    A,#9H 90H,A 34H,A 90H,A 34H,A 20H,A 90H,A 2-18 KS57C2308/P2308/C2316/P2316 ; Non-essential instruction since EMB = "0" ; (F90H) A, bank 15 is selected ; (034H) A, bank 0 is selected ; Non-essential instruction since EMB = "0" ; (F90H) A, bank 15 is selected ;...

  • Page 27

    KS57C2308/P2308/C2316/P2316 ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB).

  • Page 28

    XOR the specified bit with contents of carry flag and save the result to the carry flag Save carry flag to stack with other PSW bits Restore carry flag from stack with other PSW bits KS57C2308/P2308/C2316/P2316 Carry Flag Manipulation...

  • Page 29

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator 1. Set the carry flag to logic one: EA,#0C3H HL,#0AAH EA,HL 2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P4.0: H,#3H C,@H+0FH.3 BAND C,P3.3...

  • Page 30

    ADDRESS SPACES KS57C2308/P2308/C2316/P2316 NOTES 2-22...

  • Page 31: Addressing Modes

    KS57C2308/P2308/C2316/P2316 ADDRESSING MODES OVERVIEW The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the addressable area in the RAM is restricted to specific locations.

  • Page 32

    EMB = 0 EMB = 1 EMB = 0 SMB = 0 SMB = 1 SMB = 1 SMB = 15 Figure 3-1. RAM Address Structure KS57C2308/P2308/C2316/P2316 mema.b EMB = 1 SMB = 0 SMB = 1 SMB = 1 FB0H FBFH...

  • Page 33

    KS57C2308/P2308/C2316/P2316 EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the vector address. When a RESET EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is written to the EMB.

  • Page 34

    1-bit indirect addressing using the L register occurs, the EMB flag is set to the value contained in bit 7 of ROM RESET Affected Hardware Not applicable PSW, SCMOD, IEx, IRQx, I/O BSC, I/O KS57C2308/P2308/C2316/P2316 Program Examples A,@WX PUSH BITS BITR BTST FC3H.@L BAND...

  • Page 35

    KS57C2308/P2308/C2316/P2316 SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3-2.

  • Page 36

    Bank 15 000H–FFFH SMB = 0, 1, FB0H–FBFH Bank 15 FF0H–FFFH FC0H–FFFH Bank 15 000H–0FFH Bank 0 000H–FFFH SMB = 0, 1,15 All 1-bit KS57C2308/P2308/C2316/P2316 Memory Hardware I/O Bank Mapping – All 1-bit addressable peripherals (SMB = 15) IS0, IS1, EMB, ERB, IEx, IRQx, Pn.n...

  • Page 37

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — 1-Bit Addressing Modes 1-Bit Direct Addressing 1. If EMB = "0": AFLAG EQU 34H.3 BFLAG EQU 85H.3 CFLAG EQU 0BAH.0 BITS AFLAG BITS BFLAG BTST CFLAG BITS BFLAG BITS P3.0 2. If EMB = "1": AFLAG EQU 34H.3...

  • Page 38

    000H–0FFH Bank 0 ; Non-essential instruction, since EMB = "0" (P3) ; Non-essential instruction, since EMB = "0" ; (046H) ; (F8EH (LCON)) (P3) ; (046H) ; (08EH) KS57C2308/P2308/C2316/P2316 Memory Hardware I/O Bank Mapping – All 4-bit addressable peripherals –...

  • Page 39

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — 4-Bit Addressing Modes (Continued) 4-Bit Indirect Addressing (Example 1) 1. If EMB = "0", compare bank 0 locations 040H–046H with bank 0 locations 060H–066H: ADATA EQU BDATA EQU HL,#BDATA WX,#ADATA COMP A,@WL CPSE A,@HL SRET DECS COMP 2.

  • Page 40

    2. If EMB = "1", exchange bank 0 locations 040H–046H to bank 1 locations 160H–166H: ADATA EQU BDATA EQU HL,#BDATA WX,#ADATA TRANS LD A,@WL XCHD A,@HL TRANS 3-10 KS57C2308/P2308/C2316/P2316 ; Non-essential instruction, since EMB = "0" bank 0 (040H–046H) ; Bank 0 (060H–066H) bank 0 (040H–046H) ; Bank 1 (160H–166H)

  • Page 41

    KS57C2308/P2308/C2316/P2316 8-BIT ADDRESSING Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instruction Addressing Mode Notation Description Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection Indirect: the 8-bit address indi- cated by the memory bank selection and register HL;...

  • Page 42

    PROGRAMMING TIP — 8-Bit Addressing Modes (Continued) 8-Bit Indirect Addressing 1. If EMB = "0": ADATA EQU HL,#ADATA EA,@HL 2. If EMB = "1": ADATA EQU HL,#ADATA EA,@HL 3-12 KS57C2308/P2308/C2316/P2316 ; Non-essential instruction, since EMB = "0" (046H), E (047H) (146H), E (147H)

  • Page 43: Memory Map

    KS57C2308/P2308/C2316/P2316 MEMORY MAP MEMORY MAP OVERVIEW To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location.

  • Page 44

    Location, F8FH, is not mapped. "0" "0" TOE0 "U" "U" Location, F93H, is not mapped. “0” “0” Locations, F9BH–FAFH, are not mapped. "0" "0" "0" "0" "0" KS57C2308/P2308/C2316/P2316 Addressing Mode Bit 0 1-Bit 4-Bit "0" SRB0 – SMB0 "0" "U" “0” 8-Bit...

  • Page 45

    KS57C2308/P2308/C2316/P2316 Table 4-1. I/O Map for Memory Bank 15 (Continued) Address Register FB7H SCMOD FB8H INT (A) FBAH INT (B) FBCH INT (C) FBDH INT (D) FBEH INT (E) FBFH INT (F) FC0H BSC0 FC1H BSC1 FC2H BSC2 FC3H BSC3...

  • Page 46

    Part II of this manual, "Hardware Descriptions”, in the context of the corresponding peripheral hardware module descriptions. Memory Bank 15 Bit 3 Bit 2 Bit 1 .3/.7 .2/.6 .1/.5 .3/.7 .2/.6 .1/.5 Locations, FF8H–FFFH, are not mapped. KS57C2308/P2308/C2316/P2316 Addressing Mode Bit 0 1-Bit 4-Bit .0/.4 .0/.4 8-Bit...

  • Page 47

    KS57C2308/P2308/C2316/P2316 Register and bit IDs used for bit addressing Register ID CLMOD Clock Output Mode Control Register Identifier RESET Value Read/Write Bit Addressing CLMOD.3 CLMOD.2 CLMOD.1 - .0 R = Read-only W = Write-only R/W = Read/write Type of addressing...

  • Page 48

    Interrupt interval time (wait time): Input clock frequency: Interrupt interval time (wait time): Input clock frequency: Interrupt interval time (wait time): Input clock frequency: Interrupt interval time (wait time): KS57C2308/P2308/C2316/P2316 fxx/2 (1.02 kHz) /fxx (250 ms) fxx/2 (8.18 kHz) /fxx (31.3 ms) fxx/2 (32.7 kHz)

  • Page 49

    KS57C2308/P2308/C2316/P2316 CLMOD — Clock Output Mode Register Identifier Value RESET Read/Write Bit Addressing Enable/Disable Clock Output Control Bit Bit 2 .1–.0 Clock Source and Frequency Selection Control Bits NOTE: “fxx” is the system clock, given a clock frequency of 4.19 MHz.

  • Page 50

    INT1 pin.) Disable interrupt requests at the INT0 pin Enable interrupt requests at the INT0 pin Generate INT0 interrupt (This bit is set and cleared automatically by hardware when rising or falling edge detected at INT0 pin.) KS57C2308/P2308/C2316/P2316 FBEH...

  • Page 51

    KS57C2308/P2308/C2316/P2316 IRQ2 — INT2 Interrupt Enable/Request Flags Identifier "0" Value RESET Read/Write Bit Addressing .3–.2 Bits 3–2 INT2 Interrupt Enable Flag IRQ2 INT2 Interrupt Request Flag – "0" IRQ2 Always logic zero Disable INT2 interrupt requests at the INT2 pin...

  • Page 52

    INT4 pin.) Disable INTB interrupt requests Enable INTB interrupt requests Generate INTB interrupt (This bit is set and cleared automatically by hardware when reference interval signal received from basic timer.) KS57C2308/P2308/C2316/P2316 FB8H FB8H...

  • Page 53

    KS57C2308/P2308/C2316/P2316 IRQS — INTS Interrupt Enable/Request Flags Identifier "0" Value RESET Read/Write Bit Addressing .3–.2 Bits 3–2 INTS Interrupt Enable Flag IRQS INTS Interrupt Request Flag – "0" IRQS Always logic zero Disable INTS interrupt requests Enable INTS interrupt requests Generate INTS interrupt (This bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial I/O interface.)

  • Page 54

    INTT0 Interrupt Request Flag – 4-12 "0" IET0 IRQT0 Always logic zero Disable INTT0 interrupt requests Enable INTT0 interrupt requests Generate INTT0 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match.) KS57C2308/P2308/C2316/P2316 FBCH...

  • Page 55

    KS57C2308/P2308/C2316/P2316 IRQW — INTW Interrupt Enable/Request Flags Identifier "0" Value RESET Read/Write Bit Addressing .3–.2 Bits 3–2 INTW Interrupt Enable Flag IRQW INTW Interrupt Request Flag – NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.

  • Page 56

    Interrupt requests are triggered by a rising signal edge Interrupt requests are triggered by a falling signal edge Interrupt requests are triggered by both rising and falling signal edges Interrupt request flag (IRQ0) cannot be set to logic one KS57C2308/P2308/C2316/P2316 FB4H...

  • Page 57

    KS57C2308/P2308/C2316/P2316 IMOD1 — External Interrupt 1 (INT1) Mode Register Identifier "0" Value RESET Read/Write Bit Addressing .3–.1 Bits 3–1 External Interrupt 1 Edge Detection Control Bit "0" "0" IMOD1.0 Always logic zero Rising edge detection Falling edge detection MEMORY MAP...

  • Page 58

    External Interrupt 2 Edge Detection Selection Bit 4-16 IMOD2.2 IMOD2.1 Always logic zero Select rising edge at INT2 pin Select falling edge at KS4–KS7 Select falling edge at KS2–KS7 Select falling edge at KS0–KS7 – – Ignore selection of falling edge at KS4–KS7 KS57C2308/P2308/C2316/P2316 IMOD2.0 FB6H...

  • Page 59

    KS57C2308/P2308/C2316/P2316 — Interrupt Priority Register Identifier Value RESET Read/Write Bit Addressing Interrupt Master Enable Bit .2–.0 Interrupt Priority Assignment Bits Disable all interrupt processing Enable processing for all interrupt service requests Normal interrupt handling according to default priority settings Process INTB and INT4 interrupts at highest priority...

  • Page 60: Bias

    LCD output low, turns display off: cut off current to dividing resistor, and output port 8 latch contents. If LMOD.3 = “0”, turns display off; output port 8 latch contents; If LMOD.3 = “1”, COM and SEG output in display mode; LCD display on. KS57C2308/P2308/C2316/P2316 F8EH...

  • Page 61

    KS57C2308/P2308/C2316/P2316 LMOD — LCD Mode Register Identifier Value RESET Read/Write Bit Addressing .7–.6 LCD Output Segment and Pin Configuration Bits .5–.4 LCD Clock (LCDCK) Frequency Selection Bits NOTE: Assuming watch timer clock (fw) = 32.768 kHz. .3–.0 Duty and Bias Selection for LCD Display Segments 24–27;...

  • Page 62

    Initiate idle power-down mode Initiate stop power-down mode If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4 KS57C2308/P2308/C2316/P2316 FB3H...

  • Page 63

    KS57C2308/P2308/C2316/P2316 PMG1 — Port I/O Mode Flags (Group 1: Port 3 and 6) Identifier PM6.3 Value RESET Read/Write Bit Addressing PM6.3 P6.3 I/O Mode selection Flag PM6.2 P6.2 I/O Mode Selection Flag PM6.1 P6.1 I/O Mode Selection Flag PM6.0 P6.0 I/O Mode Selection Flag PM3.3...

  • Page 64

    Set P5 to input mode Set P5 to output mode Set P4 to input mode Set P4 to output mode Always logic zero Set P2 to input mode Set P2 to output mode Always logic zero KS57C2308/P2308/C2316/P2316 “0” FEDH, FECH “0” “0”...

  • Page 65

    KS57C2308/P2308/C2316/P2316 — N-Channel Open-Drain Mode Register Identifier PNE5.3 Value RESET Read/Write Bit Addressing PNE5.3 P5.3 N-Channel Open-Drain Configurable Bit PNE5.2 P5.2 N-Channel Open-Drain Configurable Bit PNE5.1 P5.1 N-Channel Open-Drain Configurable Bit PNE5.0 P5.0 N-Channel Open-Drain Configurable Bit PNE4.3 P4.3 N-Channel Open-Drain Configurable Bit PNE4.2...

  • Page 66

    Enable full access to data memory banks 0, 1, 2, and 15 Select register bank 0 as working register area Select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (SRB) instruction operand KS57C2308/P2308/C2316/P2316 1/4/8 1/4/8 1/4/8...

  • Page 67

    KS57C2308/P2308/C2316/P2316 PUMOD — Pull-Up Resistor Mode Register Identifier PUR7 Value RESET Read/Write Bit Addressing PUR7 Connect/Disconnect Port 7 Pull-Up Resistor Control Bit PUR6 Connect/Disconnect Port 6 Pull-Up Resistor Control Bit PUR5 Connect/Disconnect Port 5 Pull-Up Resistor Control Bit PUR4 Connect/Disconnect Port 4 Pull-Up Resistor Control Bit...

  • Page 68

    Select main system clock (fx); enable main system clock Select sub system clock (fxt); enable main system clock Select main system clock (fx); disable sub system clock Select sub system clock (fxt); disable main system clock Always logic zero KS57C2308/P2308/C2316/P2316 FB7H...

  • Page 69

    KS57C2308/P2308/C2316/P2316 SMOD — Serial I/O Mode Register Identifier Value RESET Read/Write Bit Addressing .7–.5 Serial I/O Clock Selection and SBUF R/W Status Control Bits NOTE: All kHz frequency ratings assume a system clock of 4.19MHz Bit 4 Initiate Serial I/O Operation Bit...

  • Page 70

    (65.5 kHz) fxx/2 (262 kHz) Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is cleared automatically when counting starts.) Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0 Always logic zero KS57C2308/P2308/C2316/P2316 F91H, F90H "0" "0"...

  • Page 71

    KS57C2308/P2308/C2316/P2316 — Timer Output Enable Flag Register Identifier “U” Value RESET Read/Write – Bit Addressing – Bit3 TOE0 Timer/Counter 0 Output Enable Flag .1–.0 Bits 1–0 TOE0 “U” “U” – – – – Unknown Disable timer/counter 0 output at the TCLO0 pin...

  • Page 72

    Bit Addressing WDTCF Watchdog Timer Counter Clear Flag .2–.0 Bits 2–0 NOTE: After watchdog timer is cleared by writing “1”, this bit is cleared to “0” automatically. 4-30 “0” “0” Clears the watchdog timer counter Always logic zero KS57C2308/P2308/C2316/P2316 “0” F9AH...

  • Page 73

    KS57C2308/P2308/C2316/P2316 WDMOD — Watchdog Timer Mode Register Identifier Value RESET Read/Write Bit Addressing WDMOD Watchdog Timer Enable/Disable Control Others Disable watchdog timer function Enable watchdog timer function MEMORY MAP F99H, F98H 4-31...

  • Page 74

    Normal speed; set IRQW to 0.5 seconds High-speed operation; set IRQW to 3.91 ms Select the system clock (fxx/128) as the watch timer clock Select a subsystem clock as the watch timer clock KS57C2308/P2308/C2316/P2316 (note) . If the input level is high, F89H, F88H...

  • Page 75

    KS57C2308/P2308/C2316/P2316 SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set is specifically designed to support the large register files that are typical of most KS57-series microcontrollers. The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and CPU control.

  • Page 76

    Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups First 1-Byte Instruction Instruction NOTE: The MSB value of the instruction is “0”. Second 1-Byte Instruction Operand Instruction (note) A,#im INCS INCS (note) DECS (note) A,@Rra INCS INCS (note) DECS (note) @HL,A INCS INCS (note) DECS KS57C2308/P2308/C2316/P2316 (note) Operand...

  • Page 77

    KS57C2308/P2308/C2316/P2316 Reducing Instruction Redundancy When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed, but the following redundant instructions are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecutively, the following redundant instructions are also ignored.

  • Page 78

    The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: C,(operand) BAND C,(operand) C,(operand) BXOR C,(operand) IRET KS57C2308/P2308/C2316/P2316 Address Range FB0H–FBFH FF0H–FFFH FC0H–FFFH All bits of the memory bank specified by EMB and SMB that are bit-manipulatable...

  • Page 79

    KS57C2308/P2308/C2316/P2316 ADC and SBC Instruction Skip Conditions The instructions “ADC A,@HL” and “SBC A,@HL” can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction “ADS A,#im”. If an “ADS A,#im” instruction immediately follows an “ADC A,@HL” or “SBC A,@HL” instruction in a program sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function.

  • Page 80

    E, L, H, X, W, Z, Y WX, YZ, WL SRB n mema SMB n memb memc Pn.m [(RR)] KS57C2308/P2308/C2316/P2316 Definition Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 000H–1FFFH immediate address...

  • Page 81

    KS57C2308/P2308/C2316/P2316 OPCODE DEFINITIONS Table 5-7. Opcode Definitions (Direct) Register r = Immediate data for register CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected using the PCON register.

  • Page 82

    SAM47 INSTRUCTION SET KS57C2308/P2308/C2316/P2316 HIGH-LEVEL SUMMARY This section contains a high-level summary of the SAM47 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category. These tables are a useful quick-reference resource when writing application programs.

  • Page 83

    KS57C2308/P2308/C2316/P2316 Table 5-9. CPU Control Instructions — High-Level Summary Name Operand IDLE STOP memc VENTn EMB (0,1) ERB (0,1) Table 5-10. Program Control Instructions — High-Level Summary Name Operand CPSE R,#im @HL,#im A,@HL EA,@HL EA,RR ADR14 ADR12 CALL ADR14 CALLS ADR11 –...

  • Page 84

    Rotate right through carry bit Push register pair onto stack Push SMB and SRB values onto stack Pop to register pair from stack Pop SMB and SRB values from stack KS57C2308/P2308/C2316/P2316 Bytes Cycles 2 + S 2 + S 2 + S...

  • Page 85

    KS57C2308/P2308/C2316/P2316 Table 5-12. Logic Instructions — High-Level Summary Name Operand A,#im A,@HL EA,RR RRb,EA A, #im A, @HL EA,RR RRb,EA A,#im A,@HL EA,RR RRb,EA Table 5-13. Arithmetic Instructions — High-Level Summary Name Operand A,@HL EA,RR RRb,EA A, #im EA,#imm A,@HL...

  • Page 86

    Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Load specified memory bit to carry bit Load specified indirect memory bit to carry bit KS57C2308/P2308/C2316/P2316 Bytes Cycles 1 + S 2 + S...

  • Page 87

    KS57C2308/P2308/C2316/P2316 SAM47 INSTRUCTION SET BINARY CODE SUMMARY This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM47 instruction set.

  • Page 88

    STOP memc VENTn EMB (0,1) ERB (0,1) 5-14 Binary Code a13 a12 a11 a10 KS57C2308/P2308/C2316/P2316 Operation Notation PCON.2 PCON.3 No operation n (n = 0, 1, 2, 3) PC13 – 0 memc5 – 0 + (memc + 1), 7 – 0 ROM (2 x n) 7–6...

  • Page 89

    KS57C2308/P2308/C2316/P2316 Table 5-16. Program Control Instructions — Binary Code Summary Name Operand CPSE R,#im @HL,#im A,@HL EA,@HL EA,RR ADR14 ADR12 CALL ADR14 CALLS ADR11 First Byte JR #im Binary Code a13 a12 a11 a10 a11 a10 a13 a12 a11 a10...

  • Page 90

    A,@HL XCHD A,@HL A,#im A,@RRa A,DA A,Ra 5-16 Binary Code Binary Code KS57C2308/P2308/C2316/P2316 Operation Notation PC13–8 (SP + 1) (SP) PC7–0 (SP + 2) (SP + 3) EMB,ERB (SP + 5) (SP + 4) SP + 6 PC13–8 (SP + 1) (SP) PC7–0...

  • Page 91

    KS57C2308/P2308/C2316/P2316 Table 5-17. Data Transfer Instructions — Binary Code Summary (Continued) Name Operand Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA A,@HL A,@HL EA,@WX EA,@EA PUSH Binary Code SAM47 INSTRUCTION SET Operation Notation (HL), E (HL + 1)

  • Page 92

    A, #im A, @HL EA,RR RRb,EA A,#im A,@HL EA,RR RRb,EA 5-18 Binary Code Binary Code KS57C2308/P2308/C2316/P2316 Operation Notation (SP), RR (SP + 1) SP + 2 (SRB) (SP), SMB (SP + 1), SP + 2 Operation Notation A AND im...

  • Page 93

    KS57C2308/P2308/C2316/P2316 Table 5-19. Arithmetic Instructions — Binary Code Summary Name Operand A,@HL EA,RR RRb,EA A, #im EA,#imm A,@HL EA,RR RRb,EA A,@HL EA,RR RRb,EA A,@HL EA,RR RRb,EA DECS INCS Binary Code SAM47 INSTRUCTION SET Operation Notation C, A A + (HL) + C...

  • Page 94

    BITS DA.b mema.b memb.@L @H+DA.b 5-20 Binary Code KS57C2308/P2308/C2316/P2316 Operation Notation Skip if C = 1 Skip if DA.b = 1 Skip if mema.b = 1 Skip if [memb.7–2 + L.3–2]. [L.1–0] = 1 Skip if [H + DA.3–0].b = 1 Skip if DA.b = 0...

  • Page 95

    KS57C2308/P2308/C2316/P2316 Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Continued) Name Operand BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b Second Byte mema.b Binary Code FB0H–FBFH FF0H–FFFH SAM47 INSTRUCTION SET Operation Notation DA.b...

  • Page 96

    Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Concluded) Name Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Second Byte mema.b 5-22 Binary Code FB0H–FBFH FF0H–FFFH KS57C2308/P2308/C2316/P2316 Operation Notation mema.b memb.7–2 + [L.3–2]. [L.1–0] H + [DA.3–0].b mema.b memb.7–2 + [L.3–2] . [L.1–0] [H + DA.3–0].b Bit Addresses...

  • Page 97

    KS57C2308/P2308/C2316/P2316 SAM47 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction of the SAM47 instruction set. Information is arranged in a consistent format to improve readability and for use as a quick-reference resource for application programmers.

  • Page 98

    "1" ; EA ; Jump to XXX; no skip after ADC "0" ; EA ; Jump to XXX; no skip after ADC KS57C2308/P2308/C2316/P2316 Bytes Operation Notation C, A A + (HL) + C C, EA EA + RR + C...

  • Page 99

    KS57C2308/P2308/C2316/P2316 — Add With Carry (Continued) Examples: 3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction immediately after the ADS. An ADS instruction immediately after the ADC does not skip even if an overflow occurs.

  • Page 100

    ; EA ; ADS skips on overflow, but carry flag value is not affected. ; This instruction is skipped since ADS had an overflow. ; Jump to YYY. KS57C2308/P2308/C2316/P2316 Bytes Operation Notation d0 A A + im; skip on overflow EA + imm;...

  • Page 101

    KS57C2308/P2308/C2316/P2316 — Add And Skip On Overflow (Continued) Examples: 2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and the carry flag = "0": EA,HL 3. If “ADC A,@HL” is followed by an “ADS A,#im”, the ADC skips on overflow to the instruction immediately after the ADS.

  • Page 102

    Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation A AND im A AND (HL) EA AND RR...

  • Page 103

    KS57C2308/P2308/C2316/P2316 BAND — Bit Logical And BAND C,src.b Operation: Operand C,mema.b C,memb.@L C,@H+DA.b Description: The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered.

  • Page 104

    3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG EQU H,#2H BAND C,@H+FLAG 5-30 20H.3 ; C AND FLAG (20H.3) KS57C2308/P2308/C2316/P2316...

  • Page 105

    KS57C2308/P2308/C2316/P2316 BITR — Bit Reset BITR dst.b Operation: Operand DA.b mema.b memb.@L @H+DA.b Description: A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No other bits in the destination are affected. Operand DA.b mema.b memb.@L...

  • Page 106

    NOTE: Since the BITR instruction is used for output functions, the pin names used in the examples above may change for different devices in the SAM47 product family. 5-32 L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 0A0H.0 H,#0AH @H+FLAG ; Bank 0 (AH + 0H).0 = 0A0H.0 KS57C2308/P2308/C2316/P2316 "0”...

  • Page 107

    KS57C2308/P2308/C2316/P2316 BITS — Bit Set BITS dst.b Operation: Operand DA.b mema.b memb.@L @H+DA.b Description: This instruction sets the specified bit within the destination without affecting any other bits in the destination. BITS can manipulate any bit that is addressable using direct or indirect addressing modes.

  • Page 108

    NOTE: Since the BITS instruction is used for output functions, pin names used in the examples above may change for different devices in the SAM47 product family. 5-34 L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 0A0H.0 H,#0AH @H+FLAG ; Bank 0 (AH + 0H).0 = 0A0H.0 KS57C2308/P2308/C2316/P2316 "1"...

  • Page 109

    KS57C2308/P2308/C2316/P2316 — Bit Logical OR C,src.b Operation: Operand C,mema.b C,memb.@L C,@H+DA.b Description: The specified bit of the source is logically ORed with the carry flag bit value. The value of the source is unaffected. Operand C,mema.b C,memb.@L C,@H+DA.b mema.b Examples: 1.

  • Page 110

    3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG EQU H,#2H C,@H+FLAG 5-36 20H.3 ; C OR FLAG (20H.3) KS57C2308/P2308/C2316/P2316...

  • Page 111

    KS57C2308/P2308/C2316/P2316 BTSF — Bit Test and Skip on False BTSF dst.b Operation: Operand DA.b mema.b memb.@L @H+DA.b Description: The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips the instruction which immediately follows it; otherwise the instruction following the BTSF is executed.

  • Page 112

    • BITR • • • BTSF • • • 5-38 L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 0A0H.0 H,#0AH @H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip KS57C2308/P2308/C2316/P2316...

  • Page 113

    KS57C2308/P2308/C2316/P2316 BTST — Bit Test and Skip on True BTST dst.b Operation: Operand DA.b mema.b memb.@L @H+DA.b Description: The specified bit within the destination operand is tested. If it is "1", the instruction that immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST instruction is executed.

  • Page 114

    ; If P2.0 = "1", then skip ; If P2.0 = "0", then return LABEL3 L,#0AH P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 0A0H.0 H,#0AH @H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip KS57C2308/P2308/C2316/P2316...

  • Page 115

    KS57C2308/P2308/C2316/P2316 BTSTZ — Bit Test and Skip on True; Clear Bit BTSTZ dst.b Operation: Operand mema.b memb.@L @H+DA.b Description: The specified bit within the destination operand is tested. If it is a "1", the instruction immediately following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is executed.

  • Page 116

    3. Bank 0, location 0A0H.0, is tested and EMB = "0": FLAG EQU • • • BITR • • • BTSTZ BITS 5-42 0A0H.0 H,#0AH @H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip @H+FLAG ; If 0A0H.0 = "0", then 0A0H.0 KS57C2308/P2308/C2316/P2316 "1"...

  • Page 117

    KS57C2308/P2308/C2316/P2316 BXOR — Bit Exclusive OR BXOR C,src.b Operation: Operand C,mema.b C,memb.@L C,@H+DA.b Description: The specified bit of the source is logically XORed with the carry bit value. The resultant bit is written to the carry flag. The source value is unaffected.

  • Page 118

    3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG EQU H,#2H BXOR C,@H+FLAG 5-44 20H.3 C XOR FLAG (20H.3) KS57C2308/P2308/C2316/P2316...

  • Page 119

    KS57C2308/P2308/C2316/P2316 CALL — Call Procedure CALL Operation: Operand ADR14 Description: CALL calls a subroutine located at the destination address. The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six.

  • Page 120

    SP – 3 (0FDH) SP – 2 (0FEH) SP – 1 (0FFH) (00H) 5-46 Operation Summary Call direct in page (11-bits) Binary Code PC10–PC8 PC3–PC0 PC7–PC4 KS57C2308/P2308/C2316/P2316 Bytes Operation Notation [(SP–1) (SP–2)] EMB, ERB [(SP–3) (SP–4)] PC7–0 [(SP–5) (SP–6)] PC10–8 PC13–11 PC10–0 ADR10–0...

  • Page 121

    KS57C2308/P2308/C2316/P2316 — Complement Carry Flag Operation: Operand – Description: The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa. Operand – Example: If the carry flag is logic zero, the instruction changes the value to logic one.

  • Page 122

    The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice versa. Operand Example: If the accumulator contains the value 4H (0100B), the instruction leaves the value 0BH (1011B) in the accumulator. 5-48 Operation Summary Complement accumulator (A) Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation Cycles...

  • Page 123

    KS57C2308/P2308/C2316/P2316 CPSE — Compare and Skip if Equal CPSE dst,src Operation: Operand R,#im @HL,#im A,@HL EA,@HL EA,RR Description: CPSE compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. Neither operand is affected by the comparison.

  • Page 124

    Operation Summary Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Binary Code ; "Borrow" occurs ; Skipped ; Executed KS57C2308/P2308/C2316/P2316 Bytes Operation Notation R–1; skip on borrow RR–1; skip on borrow Cycles 1 + S...

  • Page 125

    KS57C2308/P2308/C2316/P2316 — Disable Interrupts Operation: Operand – Description: Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts. Interrupts can still set their respective interrupt status latches, but the CPU will not directly service them.

  • Page 126

    If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction sets the IME bit to logic one, enabling all interrupts. 5-52 Operation Summary Enable all interrupts Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation Cycles...

  • Page 127

    KS57C2308/P2308/C2316/P2316 IDLE — Idle Operation IDLE Operation: Operand – Description: IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (PCON). After an IDLE instruction has been executed, peripheral hardware remains operative.

  • Page 128

    Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Binary Code ; 7EH ; Skip ; 7EH KS57C2308/P2308/C2316/P2316 Bytes Operation Notation R + 1; skip on carry DA + 1; skip on carry (HL) (HL) + 1; skip on carry RRb + 1;...

  • Page 129

    KS57C2308/P2308/C2316/P2316 IRET — Return From Interrupt IRET Operation: Operand – Description: IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter. The stack pointer is incremented by six and the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically restored to their pre-interrupt values.

  • Page 130

    The label “SYSCON” is assigned to the instruction at program location 07FFH. The instruction SYSCON at location 0123H will load the program counter with the value 07FFH. 5-56 Operation Summary Jump to direct address (14 bits) Binary Code a13 a12 a11 a10 KS57C2308/P2308/C2316/P2316 Bytes Operation Notation PC13–0 ADR13–0 Cycles...

  • Page 131

    KS57C2308/P2308/C2316/P2316 — Jump (Short) Operation: Operand ADR12 Description: JPS causes an unconditional branch to the indicated address with the 4 K byte program memory address space. Bits 0–11 of the program counter are replaced with the directly specified address. The destination address for this jump is specified to the assembler by a label or by an actual address in program memory.

  • Page 132

    JR #im 5-58 Operation Summary Branch to relative immediate address Branch relative to contents of WX register Branch relative to contents of EA Binary Code First Byte KS57C2308/P2308/C2316/P2316 Bytes Operation Notation PC13–0 ADR (PC–15 to PC+16) PC13–0 PC13–8 + (WX) PC13–0 PC13–8 + (EA)

  • Page 133

    KS57C2308/P2308/C2316/P2316 — Jump Relative (Very Short) (Continued) Examples: 1. A short form for a relative jump to label “KK” is the instruction JR KK where “KK” must be within the allowed range of current PC–15 to current PC+16. The JR instruction has in this case the effect of an unconditional JP instruction.

  • Page 134

    Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation d0 A (RRa) Cycles...

  • Page 135

    KS57C2308/P2308/C2316/P2316 — Load (Continued) Description: Operand RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA Examples: 1. RAM location 30H contains the value 4H. The RAM location values are 40H, 41H and 0AH, 3H respectively. The following instruction sequence leaves the value 40H in point pair HL, 0AH in the accumulator and in RAM location 40H, and 3H in register E.

  • Page 136

    Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a redundancy effect if the operation addresses the HL or EA registers. Load contents of register A to direct data memory address. Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y). KS57C2308/P2308/C2316/P2316...

  • Page 137

    KS57C2308/P2308/C2316/P2316 — Load (Concluded) Examples: Instruction LD EA,@HL Load data memory contents pointed to by 8-bit register HL to the A register, LD EA,DA LD EA,RRb LD @HL,A LD DA,EA LD RRb,EA LD @HL,EA Load the A register to data memory location pointed to by the 8-bit HL Operation Description and Guidelines and the contents of HL+1 to the E register.

  • Page 138

    Load carry bit to a specified indirect memory bit Load memory bit to a specified carry bit Load indirect memory bit to a specified carry bit Binary Code Second Byte KS57C2308/P2308/C2316/P2316 Bytes Operation Notation mema.b memb.7–2 + [L.3–2]. [L.1–0] H + [DA.3–0].b mema.b...

  • Page 139

    KS57C2308/P2308/C2316/P2316 — Load Bit (Continued) Examples: 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. C,P1.0 2. The P1 address is FF1H and the L register contains the value 9H (1001B). The address (memb.7–2) is 111100B and (L.3–2) is 10B.

  • Page 140

    Operation Summary Load code byte from WX to EA Load code byte from EA to EA Binary Code EA,#00H CALL DISPLAY MAIN 0500H EA,@EA ; EA KS57C2308/P2308/C2316/P2316 Bytes Operation Notation [PC13–8 + (WX)] [PC13–8 + (EA)] address 0500H = 66H Cycles...

  • Page 141

    KS57C2308/P2308/C2316/P2316 — Load Code Byte (Continued) Examples: 2. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: DISPLAY If the instruction “LD WX,#01H” is executed in place of “LD WX,#00H”, then address 0501H = 77H.

  • Page 142

    Operation Summary Load indirect data memory contents to A; decrement register L contents and skip on borrow Binary Code (HL) and L ; Skip 2H and L KS57C2308/P2308/C2316/P2316 Bytes Operation Notation (HL), then L skip if L = 0FH L–1 Cycles 2 + S L–1;...

  • Page 143

    KS57C2308/P2308/C2316/P2316 — Load Data Memory and Increment dst,src Operation: Operand A,@HL Description: The contents of a data memory location are loaded into the accumulator, and the contents of the register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is 0H), the next instruction is skipped.

  • Page 144

    PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction. Operand – Example: Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power-down mode is initiated: STOP 5-70 Operation Summary No operation Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation No operation Cycles...

  • Page 145

    KS57C2308/P2308/C2316/P2316 — Logical OR dst,src Operation: Operand A, #im A, @HL EA,RR RRb,EA Description: The source operand is logically ORed with the destination operand. The result is stored in the destination. The contents of the source are unaffected. Operand A, #im...

  • Page 146

    0EFH and the data pointer pair HL set to 34H. 5-72 Operation Summary Pop to register pair from stack Pop SMB and SRB values from stack Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation (SP), RR SP+2 (SRB)

  • Page 147

    KS57C2308/P2308/C2316/P2316 PUSH — Push Onto Stack PUSH Operation: Operand Description: The SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer, thereby adding a new element to the top of the stack.

  • Page 148

    The carry flag is cleared to logic zero, regardless of its previous value. Operand – Example: Assuming the carry flag is set to logic one, the instruction resets (clears) the carry flag to logic zero. 5-74 Operation Summary Reset carry flag to logic zero Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation Cycles...

  • Page 149

    KS57C2308/P2308/C2316/P2316 — Reference Instruction Operation: Operand memc NOTE The instruction referenced by REF determines the instruction cycles. Description: The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the REF instruction reference area in program memory. REF reduces the number of program memory accesses for a program.

  • Page 150

    “redundancy effect”: • • • • • • 5-76 0020H HL,#00H EA,#FFH SUB1 SUB2 ; LD HL,#00H ; LD EA,#FFH ; CALL SUB1 ; JP SUB2 0020H EA,#40H 0100H EA,#30H ; Not skipped EA,#50H ; Skipped KS57C2308/P2308/C2316/P2316...

  • Page 151

    KS57C2308/P2308/C2316/P2316 — Reference Instruction (Concluded) Examples: 3. In this example the binary code of “REF A1” at locations 20H–21H is 20H, for “REF A2” at locations 22H–23H, it is 21H, and for “REF A3” at 24H–25H, the binary code is 22H :...

  • Page 152

    SP + 2(0FCH) SP + 3(0FDH) SP + 4(0FEH) SP + 5(0FFH) SP + 6(00H) 5-78 Operation Summary Return from subroutine Binary Code PC11–PC8 PC13 PC12 PC3–PC0 PC7–PC4 KS57C2308/P2308/C2316/P2316 Bytes Operation Notation PC13–8 (SP+1) (SP) PC7–0 (SP+2) (SP+3) EMB,ERB SP+6 Cycles...

  • Page 153

    KS57C2308/P2308/C2316/P2316 — Rotate Accumulator Right Through Carry Operation: Operand Description: The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position.

  • Page 154

    Binary Code "1" ; EA ; Jump to XXX; no skip after SBC "0" ; EA ; Jump to XXX; no skip after SBC KS57C2308/P2308/C2316/P2316 Bytes Operation Notation A – (HL) – C C, EA EA –RR – C C,RRb RRb –...

  • Page 155

    KS57C2308/P2308/C2316/P2316 — Subtract With Carry (Continued) Examples: 3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on “no borrow” to the instruction immediately after the ADS. An “ADS A,#im” instruction immediately after the “SBC A,@HL” instruction does not skip even if an overflow occurs. This function is useful for decimal adjustment operations.

  • Page 156

    ; Jump to YYY is executed "1" ; EA ; Jump to XXX ; JPS was not skipped since no "borrow" occurred after KS57C2308/P2308/C2316/P2316 Bytes Operation Notation A – (HL); skip on borrow EA – RR; skip on borrow RRb – EA; skip on borrow 0C3H –...

  • Page 157

    KS57C2308/P2308/C2316/P2316 — Set Carry Flag Operation: Operand – Description: The SCF instruction sets the carry flag to logic one, regardless of its previous value. Operand – Example: If the carry flag is cleared to logic zero, the instruction sets the carry flag to logic one.

  • Page 158

    0 (000H–0FFH) as the working memory bank. 5-84 Operation Summary Select memory bank Register Areas Working registers Stack and general-purpose registers General-purpose registers I/O-mapped hardware registers Binary Code KS57C2308/P2308/C2316/P2316 Bytes Bank (n = 1–14) Operation Notation Cycles (n = 1–14)

  • Page 159

    KS57C2308/P2308/C2316/P2316 — Select Register Bank Operation: Operand Description: The SRB instruction selects one of four register banks in the working register memory area. The constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB...

  • Page 160

    SP + 6(00H) 5-86 Operation Summary Return from subroutine and skip Binary Code PC11–PC8 PC13 PC12 PC3–PC0 PC7–PC4 KS57C2308/P2308/C2316/P2316 Bytes Operation Notation PC13–8 (SP + 1) (SP) PC7–0 (SP + 3) (SP + 2) EMB,ERB (SP + 4) SP + 6...

  • Page 161

    KS57C2308/P2308/C2316/P2316 STOP — Stop Operation STOP Operation: Operand – Description: The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one. When STOP executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions.

  • Page 162

    (ERB) and program counter to vector address, then branch to the corresponding location. d1,d2,ADDR Binary Code a13 a12 a11 a10 KS57C2308/P2308/C2316/P2316 Bytes Operation Notation ROM (2 x n) 7–6 ROM (2 x n) 5–4 ROM (2 x n) 3–0 ROM (2 x n + 1) 7–0...

  • Page 163

    KS57C2308/P2308/C2316/P2316 VENT — Load EMB, ERB, and Vector Address VENTn (Continued) Example: The instruction sequence 0000H VENT0 1,0,RESET VENT1 0,1,INTA VENT2 0,1,INTB • • • VENT7 0,1,INTG causes the program sequence to branch to the and ERB to "0" when causes the program to branch to the basic timer's interrupt service routine, INTA, and to set the EMB value to "0"...

  • Page 164

    Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Binary Code KS57C2308/P2308/C2316/P2316 Bytes Operation Notation (RRa) DA,E DA + 1...

  • Page 165

    KS57C2308/P2308/C2316/P2316 XCHD — Exchange and Decrement XCHD dst,src Operation: Operand A,@HL Description: The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L. If the content of register L is 0FH, the next instruction is skipped.

  • Page 166

    HL,#2FH A,#0H A,@HL 0FH and L ; Skipped since an overflow occurred 2H, L A,@HL ; (20H) KS57C2308/P2308/C2316/P2316 Bytes Operation Notation (HL), then L skip if L = 0H L + 1 = 0, (HL) "0" 0FH, A (20H), L...

  • Page 167

    KS57C2308/P2308/C2316/P2316 — Logical Exclusive OR dst,src Operation: Operand A,#im A,@HL EA,RR RRb,EA Description: XOR performs a bitwise logical XOR operation between the source and destination variables and stores the result in the destination. The source contents are unaffected. Operand A,#im...

  • Page 168

    SAM47 INSTRUCTION SET KS57C2308/P2308/C2316/P2316 NOTES 5-94...

  • Page 169

    Oscillator Circuits Interrupts Power-Down RESET I/O Ports Timers and Timer/Counters LCD Controller/Driver Electrical Data Mechanical Data KS57P2308/P2316 OTP...

  • Page 171

    OSCILLATOR CIRCUITS OVERVIEW The KS57C2308/C2316 microcontroller has two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. Specifically, a clock pulse is required by the following peripheral modules: —...

  • Page 172

    OSCILLATOR CIRCUITS KS57C2308/P2308/C2316/P2316 Clock Control Registers When the system clock mode control register, SCMOD, and the power control register, PCON, are both cleared to zero after , the normal CPU operating mode is enabled, a main system clock of fx/64 is selected, and RESET main system clock oscillation is initiated.

  • Page 173

    KS57C2308/P2308/C2316/P2316 Main-System Oscillator Circuit X IN X OUT Oscillator Stop SCMOD.3 SCMOD.0 SCMOD.2 PCON.0 PCON.1 IDLE PCON.2 PCON.3 fx: Main-system clock fxt: Sub-system clock fxx: System clock Selector Oscillator Stop 1/8 - 1/4096 Frequency Dividing Circuit 1/16 Selector fx/1,2,16 Oscillator...

  • Page 174

    Figure 6-3. External Oscillator Figure 6-4. RC Oscillator SUBSYSTEM OSCILLATOR CIRCUITS X IN X OUT X IN X OUT X IN X OUT KS57C2308/P2308/C2316/P2316 XT IN XT OUT 32.768 kHz Figure 6-5. Crystal/Ceramic Oscillator XT IN External Clock XT OUT...

  • Page 175

    KS57C2308/P2308/C2316/P2316 POWER CONTROL REGISTER (PCON) The power control register (PCON) is a 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. The PCON can be addressed directly by 4-bit write instructions or indirectly by the instructions IDLE and STOP.

  • Page 176

    Table 6-2. Instruction Cycle Times for CPU Clock Rates Oscillation Source fx = 4.19 MHz fxt = 32.768 kHz Selected Resulting CPU Clock Frequency fx/64 65.5 kHz fx/8 524.0 kHz fx/4 1.05 MHz fxt/4 8.19 kHz KS57C2308/P2308/C2316/P2316 Cycle Time (µs) 15.3 1.91 0.95 122.0...

  • Page 177

    KS57C2308/P2308/C2316/P2316 SYSTEM CLOCK MODE REGISTER (SCMOD) The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control main and sub-system clock oscillation. SCMOD is mapped to the RAM address FB7H.

  • Page 178

    Sub oscillator stops. Set SCMOD.2 to “1” Main oscillator still runs (stops). Sub oscillator stops, halting the CPU operation. KS57C2308/P2308/C2316/P2316 Osc Stop Release Source Interrupt and reset: After releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. And then the CPU operates.

  • Page 179

    KS57C2308/P2308/C2316/P2316 Mode Main operating mode Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Main Idle mode Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Main Stop mode Main oscillator runs.

  • Page 180

    , CPU operation starts with the lowest main system clock frequency of 15.3 µs at 4.19 MHz after the RESET standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-6 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect. 6-10 KS57C2308/P2308/C2316/P2316 NOTE...

  • Page 181

    KS57C2308/P2308/C2316/P2316 Table 6-6. Elapsed Machine Cycles During CPU Clock Switch AFTER BEFORE PCON.1 = 0 PCON.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 8 MACHINE CYCLES PCON.0 = 0...

  • Page 182

    Resulting Clock Output Clock Source CPU clock (fx/4, fx/8, fx/64, fxt/4) fxx/8 fxx/16 fxx/64 Result of CLMOD.3 Setting Clock output is disabled Clock output is enabled KS57C2308/P2308/C2316/P2316 CLMOD Frequency 1.05 MHz, 524 kHz, 65.5 kHz 524 kHz 262 kHz 65.5 kHz...

  • Page 183

    KS57C2308/P2308/C2316/P2316 CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: — 4-bit clock output mode register (CLMOD) — Clock selector — Port mode flag — CLO output pin (P2.2) CLMOD.3...

  • Page 184

    OSCILLATOR CIRCUITS PROGRAMMING TIP — CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin: BITS EA,#04H PMG2,EA BITR P2.2 A,#9H CLMOD,A 6-14 KS57C2308/P2308/C2316/P2316 ; P2 Output mode ; Clear P2.2 pin output latch...

  • Page 185

    KS57C2308/P2308/C2316/P2316 INTERRUPTS OVERVIEW The KS57C2308/C2316 interrupt control circuit has five functional components: — Interrupt enable flags (IEx) — Interrupt request flags (IRQx) — Interrupt master enable register (IME) — Interrupt priority register (IPR) — Power-down release signal circuit Three kinds of interrupts are supported: —...

  • Page 186

    INTERRUPTS KS57C2308/P2308/C2316/P2316 Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. A vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (INTn) are set to logic one: —...

  • Page 187

    KS57C2308/P2308/C2316/P2316 Generates the corresponding vector IS1,0 = 0,1 Stores the contents of PC and PSW in stack area; set PC contents to corresponding vector address. Reset corresponding IRQx flag Jump to interrupt start address Interrupt is generated. ( INT xx) Request flag (IRQx) <-- 1...

  • Page 188

    Power-Down Mode Release Signal IS1 IS0 # = Noise Filtering Circuit @ = Edge Detection Circuit IRQB INTB IRQ4 IRQ0 IRQ1 IRQS IRQT0 IRQW IRQ2 Figure 7-2. Interrupt Control Circuit Diagram KS57C2308/P2308/C2316/P2316 IET0 IES IE1 Interrupt Control Unit Vector Interrupt Generator...

  • Page 189

    KS57C2308/P2308/C2316/P2316 MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine.

  • Page 190

    Interrupt INT Disable Status 1 Modify Status INT Enable Status 0 Low or High Level Interrupt Generated Status 0 Figure 7-4. Multi-Level Interrupt Handling KS57C2308/P2308/C2316/P2316 After INT ACK – – 2-Level Interrupt 3-Level Interrupt High-Level Status 1 Status 2 Interrupt Generated –...

  • Page 191

    KS57C2308/P2308/C2316/P2316 INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction.

  • Page 192

    "0" "0" IMOD1.0 IMOD2.1 IMOD2.0 IMOD0.1 IMOD0.0 IMOD1.0 KS57C2308/P2308/C2316/P2316 clears all IMOD values to logic RESET Effect of IMOD0 Settings Select CPU clock for sampling Select fxx/64 sampling clock Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1"...

  • Page 193

    KS57C2308/P2308/C2316/P2316 EXTERNAL INTERRUPT0 and INTERRUPT1 MODE REGISTERS (Continued) When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: —...

  • Page 194

    7-10 IMOD2.1 IMOD2.0 Table 7-6. IMOD2 Register Bit Settings IMOD2.1 IMOD2.0 KS57C2308/P2308/C2316/P2316 Effect of IMOD2 Settings Select rising edge at INT2 pin Select falling edge at KS4–KS7 Select falling edge at KS2–KS7 Select falling edge at KS0–KS7 Ignore selection of falling edge at KS4–KS7...

  • Page 195

    KS57C2308/P2308/C2316/P2316 INTERRUPTS RISING EDGE INT2 DETECTION CIRCUIT FALLING EDGE DETECTION CIRCUIT CLOCK IRQ2 SELECTOR IMOD2 Figure 7-6. Circuit Diagram for INT2 and KS0–KS7 Pins 7-11...

  • Page 196

    IEx = 0 is interrupt disable mode. IEx = 1 is interrupt enable mode. 7-12 IPR.1 IPR.0 Inhibit all interrupts Enable all interrupts Bit 3 Bit 2 IRQ4 IRQ1 KS57C2308/P2308/C2316/P2316 Effect of Bit Settings Bit 1 Bit 0 IRQB IRQW IET0 IRQT0 IRQS IRQ0 IRQ2...

  • Page 197

    KS57C2308/P2308/C2316/P2316 Interrupt Request Flags (IRQx) Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag. When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then automatically cleared to logic zero when the interrupt has been serviced.

  • Page 198

    To simultaneously enable INTB and INT4 interrupts: INTB BTSTZ IRQB INT4 • • • IRET INT4 BITR IRQ4 • • • IRET 7-14 KS57C2308/P2308/C2316/P2316 ; IRQB = 1 ? ; If no, INT4 interrupt; if yes, INTB interrupt is processed ; INT4 is processed...

  • Page 199

    POWER-DOWN OVERVIEW The KS57C2308/C2316 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally.

  • Page 200

    TCL0 is selected as counter clock. Watch timer stops. LCD controller stops. INT0, INT1, and INT2 is not serviced. Only input RESET KS57C2308/P2308/C2316/P2316 Main/Sub Stop Main (fx) or sub clock Main clock (fx) (fxt) STOP IDLE Main clock oscillation Only CPU clock stops stops.

  • Page 201

    KS57C2308/P2308/C2316/P2316 IDLE MODE TIMING DIAGRAMS RESET NORMAL MODE CLOCK SIGNAL Figure 8-1. Timing When Idle Mode is Released by MODE RELEASE SIGNAL NORMAL MODE CLOCK SIGNAL Figure 8-2. Timing When Idle Mode is Released by an Interrupt IDLE INSTRUCTION IDLE MODE...

  • Page 202

    POWER-DOWN KS57C2308/P2308/C2316/P2316 STOP MODE TIMING DIAGRAMS OSCILLATION STOP STABILIZATION INSTRUCTION (31.3 ms / 4.19 MHz) RESET NORMAL MODE STOP MODE IDLE MODE NORMAL MODE OSCILLATION STOPS OSCILLATION RESUMES CLOCK SIGNAL Figure 8-3. Timing When Stop Mode is Released by RESET...

  • Page 203

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. In this example, the system clock source is switched from the main system clock to a subsystem clock and the LCD...

  • Page 204

    – 0.7 V. In this case, total current consumption would not be reduced. 5. Determine the correct output pin state necessary to block current pass in according with the external transistors (PNP, NPN). KS57C2308/P2308/C2316/P2316 or V levels in order to check the current input...

  • Page 205

    KS57C2308/P2308/C2316/P2316 RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 8-2. Table 8-2. Unused Pin Connections for Reducing Power Consumption Pin/Share Pin Names P0.0/INT4 P0.1/ P0.2/SO P0.3/SI P1.0/INT0 P1.1/INT1...

  • Page 206

    POWER-DOWN KS57C2308/P2308/C2316/P2316 NOTES...

  • Page 207

    KS57C2308/P2308/C2316/P2316 RESET OVERVIEW When a signal is input during normal operation or power-down mode, a hardware reset operation is RESET initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has elapsed, normal system operation resumes.

  • Page 208

    Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Values retained 0, 0 KS57C2308/P2308/C2316/P2316 occurs during power-down RESET RESET Occurs During RESET Normal Operation Lower five bits of address 0000H are transferred to PC12/13–8,...

  • Page 209

    KS57C2308/P2308/C2316/P2316 Table 9-1. Hardware Register Values After Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD) Port N-ch open drain reg (PNE) Basic Timer: Count register (BCNT) Mode register (BMOD)

  • Page 210

    KS57C2308/P2308/C2316/P2316 RESET NOTES...

  • Page 211

    I/O PORTS OVERVIEW The KS57C2308/C2316 has 9 ports. There are total of 8 input pins, 8 output pin and 24 configurable I/O pins, for a maximum number of 40 pins. Pin addresses for all ports are mapped to bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions.

  • Page 212

    P2.3 Output latch contents undefined P2,A Transfer accumulator data to the P6,EA output latch KS57C2308/P2308/C2316/P2316 Function Description 4-bit input port. 1-bit and 4-bit read and test are possible. P0.1 and P0.2 are software configurable as input or output for and SO by SMOD register.

  • Page 213

    KS57C2308/P2308/C2316/P2316 PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. For convenient program reference, PM flags are organized into two groups — PMG1 and PMG2 as shown in Table 10-3.

  • Page 214

    ; enable the pull-up resistors of P2 and P3 PNE4.1 PNE4.0 PNE5.1 PNE5.0 LCD Output Segments Seg 24–31 Seg 24–27 Seg 28–31 – , the values contained in the port 8 output RESET KS57C2308/P2308/C2316/P2316 1-Bit Output Pins – P8.4–P8.7 (Seg 28–31) P8.0–P8.3 (Seg 24–27) P8.0–P8.7 (Seg 24–31)

  • Page 215

    KS57C2308/P2308/C2316/P2316 Table 10-6. Port 8 Pin Addresses and LCD Segment Correspondence Port 8 Pin Number P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 RAM Address LCD Segment 1F8H SEG24 1F9H SEG25 1FAH SEG26 1FBH SEG27 1FCH SEG28 1FDH SEG29 1FEH...

  • Page 216

    (PUMOD). 10-6 and SO act as an output, its pull-up resistor is automatically Figure 10-1. Port 0 Circuit Diagram KS57C2308/P2308/C2316/P2316 INT4 SMOD...

  • Page 217

    KS57C2308/P2308/C2316/P2316 PORT 1 CIRCUIT DIAGRAM PUMOD.1 P1.0 P1.1 P1.2 P1.3 INT0 Noise Filter CPU clock INT1 IMOD0 Circuit Clock Selector fxx/64 P1.1 P1.0 Figure 10-2. Port 1 Circuit Diagram INT0 INT1 INT2 TCL0 Edge Detection IRQ0 IRQ1 Edge Detection IMOD0...

  • Page 218

    When a port pin acts as an output, its pull-up resistor is automatically NOTE: disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD). 10-8 Figure 10-3. Port 2 Circuit Diagram KS57C2308/P2308/C2316/P2316 TCLO0 Output Latch 1, 4 1, 4...

  • Page 219

    KS57C2308/P2308/C2316/P2316 PORT 3 AND 6 CIRCUIT DIAGRAM PUMOD.x Px.0 Px.1 Px.2 Px.3 NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

  • Page 220

    (PUMOD). 10-10 PNEx.3 PNEx.2 PNEx.1 PNEx.0 CMOS Push-Pull or N-Channel Open-Deain Figure 10-5. Port 4 and 5 Circuit Diagram KS57C2308/P2308/C2316/P2316 x = port number (4, 5) PM.x Output 1, 4, 8 Latch 1, 4, 8...

  • Page 221

    KS57C2308/P2308/C2316/P2316 PORT 7 CIRCUIT DIAGRAM PUMOD.7 P7.0 P7.1 P7.2 P7.3 NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

  • Page 222

    I/O PORTS KS57C2308/P2308/C2316/P2316 NOTES 10-12...

  • Page 223

    KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS TIMERS and TIMER/COUNTERS OVERVIEW The KS57C2308/C2316 microcontroller has three timer and timer/counter modules: — 8-bit basic timer (BT) — 8-bit timer/counter (TC0) — Watch timer (WT) The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register.

  • Page 224

    TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 BASIC TIMER (BT) OVERVIEW The 8-bit basic timer (BT) has five functional components: — Clock selector logic — 4-bit mode register (BMOD) — 8-bit counter register (BCNT) — 8-bit watchdog timer mode register (WDMOD) — Watchdog timer counter clear flag (WDTCF) The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.

  • Page 225

    KS57C2308/P2308/C2316/P2316 Register Type Name BMOD Control Controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or BCNT Counter Counts clock pulses matching the BMOD frequency setting WDMOD Control Controls watchdog timer operation.

  • Page 226

    Basic Timer Input Clock fxx/2 (1.02 kHz) fxx/2 (8.18 kHz) fxx/2 (32.7 kHz) fxx/2 (131 kHz) KS57C2308/P2308/C2316/P2316 and interrupt request signal generation RESET to fxx/2 , are selectable. Since BMOD's Basic Timer Restart Bit Interval Time /fxx (250 ms) /fxx (31.3 ms) /fxx (7.82 ms)

  • Page 227

    KS57C2308/P2308/C2316/P2316 BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. leaves the BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the RESET BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected.

  • Page 228

    ; Wait time is 31.3 ms ; Get into stop for power-down mode STOP MODE STOP STOP MODE IS INSTRUCTION RELEASED BY INTERRUPT ; Basic timer interrupt enable flag is set to "1" KS57C2308/P2308/C2316/P2316 NORMAL IDLE MODE OPERATING MODE (31.3 ms)

  • Page 229

    KS57C2308/P2308/C2316/P2316 WATCHDOG TIMER MODE REGISTER (WDMOD) The watchdog timer mode register, WDMOD, is a 8-bit write-only register located at RAM address F98H–F99H. WDMOD register controls to enable or disable the watchdog function. WDMOD values are set to logic “A5H” following...

  • Page 230

    PROGRAMMING TIP — Using the Watchdog Timer RESET BITS EA,#00H SP,EA A,#0DH BMOD,A MAIN BITS WDTCF MAIN 11-8 KS57C2308/P2308/C2316/P2316 ; WDCNT input clock is 7.82 ms ; Main routine operation period must be shorter than ; watchdog ; timer’s period...

  • Page 231

    KS57C2308/P2308/C2316/P2316 8-BIT TIMER/COUNTER 0 (TC0) OVERVIEW Timer/counter 0 (TC0) is used to count system “events” by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request.

  • Page 232

    Cleared when TC0 operation starts and the TC0 interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide. Must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed. KS57C2308/P2308/C2316/P2316...

  • Page 233

    KS57C2308/P2308/C2316/P2316 Register Type Name TMOD0 Control Controls TC0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6–4) TCNT0 Counter Counts clock pulses matching the TMOD0 frequency setting TREF0 Reference Stores reference value for the...

  • Page 234

    TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 — Set TMOD0.2 to logic one — Set the TC0 interrupt enable flag IET0 to logic one — Set TMOD0.3 to logic one TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.

  • Page 235

    KS57C2308/P2308/C2316/P2316 TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock frequency.

  • Page 236

    — Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin; — Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5 and TMOD0.4. Table 11-5. TMOD0 Settings for TCL0 Edge Detection TMOD0.5 11-14 TMOD0.4 TCL0 Edge Detection Rising edges Falling edges KS57C2308/P2308/C2316/P2316...

  • Page 237

    KS57C2308/P2308/C2316/P2316 TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected by loading the desired reference value into the reference register TREF0.

  • Page 238

    Output external TCL0 clock pulse to the TCLO0 pin (divided by four): EXTERNAL (TCL0) CLOCK PULSE TCLO0 OUTPUT PULSE BITS EA,#01H TREF0,EA EA,#0CH TMOD0,EA EA,#04H PMG2,EA BITR P2.0 BITS TOE0 11-16 KS57C2308/P2308/C2316/P2316 ; P2.0 output mode ; Clear P2.0 output latch...

  • Page 239

    KS57C2308/P2308/C2316/P2316 TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. F90H TMOD0.3 TMOD0.2 F91H "0" TMOD0.6 TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0"...

  • Page 240

    2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation: BITS BITS TMOD0.3 11-18 TMOD0.4 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fxx/2 (4.09 kHz) fxx /2 (16.4 kHz) fxx/2 (65.5 kHz) fxx/2 (262 kHz) KS57C2308/P2308/C2316/P2316...

  • Page 241

    KS57C2308/P2308/C2316/P2316 TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control instructions. sets all TCNT0 register values to logic zero (00H). RESET Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. TCNT0 register value is incremented at the selected edge each time an incoming pulse with reference clock specified by TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4) is input.

  • Page 242

    TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control instructions. initializes the TREF0 value to “FFH”. RESET TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval.

  • Page 243

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — Setting a TC0 Timer Interval To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter...

  • Page 244

    TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 WATCH TIMER OVERVIEW The watch timer is a multi-purpose timer which consists of three basic components: — 8-bit watch timer mode register (WMOD) — Clock selector — Frequency divider circuit Watch timer functions include real-time and watch-time measurement and interval timing for the main and subsystem clock.

  • Page 245

    KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the desired BUZ frequency, load the appropriate value to the WMOD register. This output can then be used to actuate an external buzzer sound.

  • Page 246

    (32.768 kHz) fx = Main System Clock (4.19 MHz) fxt = Subsystem Clock (32.768 kHz) fxx/128 fw = Watch Timer Frequency fxx = System Clock Figure 11-4. Watch Timer Circuit Diagram KS57C2308/P2308/C2316/P2316 P2.3 fw/4 fw/8 (4 kHz) Selector Circuit fw/16...

  • Page 247

    KS57C2308/P2308/C2316/P2316 WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only addressable. An exception is WMOD bit 3 (the XT automatically sets WMOD.3 to the current input level of the subsystem clock, XT RESET low, if logic zero), and all other WMOD bits to logic zero.

  • Page 248

    2. Sample real-time clock processing method: CLOCK BTSTZ • • • 11-26 EA,#04H PMG2,EA ; P2.3 P2.3 EA,#85H WMOD,EA IRQW ; 0.5 second check ; No, return ; Yes, 0.5 second interrupt generation ; Increment HOUR, MINUTE, SECOND KS57C2308/P2308/C2316/P2316 output mode...

  • Page 249

    KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIVER OVERVIEW The KS57C2308/C2316 microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel. Its LCD block has the following components: — LCD controller/driver — Display RAM for storing display data — 32 segment output pins (SEG0–SEG31) —...

  • Page 250

    1F4H.3 1F4H.2 1F4H.1 1F4H.0 1E0H.3 1E0H.2 1E0H.1 1E0H.0 LMOD LCON 12-2 f LCD TIMING CONTROLLER Port 3 latch Figure 12-2. LCD Circuit Diagram KS57C2308/P2308/C2316/P2316 SEG31/P8.7 SEG30/P8.6 SEG29/P8.5 SEG28/P8.4 SEG27/P8.3 SEG26/P8.2 SEG25/P8.1 SEG24/P8.0 SEG23 SEG22 SEG21 SEG20 SEG19 SEG0 COM3 COM2...

  • Page 251

    KS57C2308/P2308/C2316/P2316 LCD RAM ADDRESS AREA RAM addresses of bank 1 are used as LCD data memory. These locations can be addressed by 1-bit, 4-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.

  • Page 252

    Table 12-3. LCON.0 and LMOD.3 Bit Settings COM0–COM3 SEG0–SEG31 Output low; LCD display off LCD display off Output latch SEG output corresponds to display mode KS57C2308/P2308/C2316/P2316 LCON.0 F8EH Description P8.0–P8.7 Output latch Cut off current to contents dividing resistors LCD display off...

  • Page 253

    KS57C2308/P2308/C2316/P2316 LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and display on/off. LMOD can be manipulated using 8-bit write instructions, bit 3 (LMOD.3) can be also written by 1-bit instructions.

  • Page 254

    256 (128) Static Mode 1/2 Bias 2/3 V 1/2 V 1/3 V 1/2 V pin so that it can handle the different LCD drive KS57C2308/P2308/C2316/P2316 1/3 Duty 1/4 Duty 21 (21) 43 (43) 85 (85) 171 (171) 128 (128) 1/3 Bias...

  • Page 255

    KS57C2308/P2308/C2316/P2316 Static and 1/3 Bias (V LCD = 3 V at V DD = 5 V) LCON.0 = 3 V Static and 1/3 Bias (V LCD = 5 V at V DD = 5 V) Static and 1/3 Bias (V LCD = 3 V at V DD = 3 V) LCON.0...

  • Page 256

    NOTE: “NC” means that no connection is required. COM0 Figure 12-5. LCD Common Signal Waveform (Static) 12-8 COM0 Pin COM1 Pin Selected Selected Selected Selected Selected Selected Selected T: LCDCK : Frame frequency KS57C2308/P2308/C2316/P2316 COM2 Pin COM3 Pin Selected Selected Selected...

  • Page 257

    KS57C2308/P2308/C2316/P2316 COM0, 1 (1/2 DUTY) COM0, 1 (1/3 DUTY) Figure 12-6. LCD Common Signal Waveform at 1/2 Bias (1/2, 1/3 Duty) = 2 x T = 3 x T T: LCDCK : Frame frequency LCD CONTROLLER/DRIVER LC1, 2 LC1, 2...

  • Page 258

    LCD CONTROLLER/DRIVER COM0-2 (1/3 DUTY) COM0-3 (1/4 DUTY) Figure 12-7. LCD Common Signal Waveform at 1/3 Bias (1/3, 1/4 Duty) 12-10 = 3 x T = 4 x T T: LCDCK : Frame frequency KS57C2308/P2308/C2316/P2316...

  • Page 259

    KS57C2308/P2308/C2316/P2316 SEGMENT (SEG) SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at 1E0H–1FFH. Bits 0–3 of the display RAM are synchronized with the common signal output pins COM0, COM1, COM2, and COM3. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.

  • Page 260

    Non-select Figure 12-9. Select/No-select Bias Signals in 1/2 Bias Display Mode 12-12 –V – 1/2 V SELECT NO-SELECT T: LCDCK KS57C2308/P2308/C2316/P2316 Select Non-select / + V 0 V/ 0 V / + 1/2 VLCD + 1/2 V LC1, 2 LC1, 2...

  • Page 261

    KS57C2308/P2308/C2316/P2316 Table 12-9. Select/No-Select Signals for LCD 1/3 Bias Display Mode Select Non-select Figure 12-10. Select/No-select Bias Signals in 1/3 Bias Display Mode –V – 1/3 V SELECT NO-SELECT T: LCDCK LCD CONTROLLER/DRIVER Select Non-select / + V 0 V/ 0 V...

  • Page 262

    LCD CONTROLLER/DRIVER COM0 SEG11 SEG12 COM0– SEG11 COM0– SEG12 Figure 12-11. LCD Signal Waveforms in Static Mode 12-14 KS57C2308/P2308/C2316/P2316 V LC0 V SS V LC0 V SS V LC0 V SS +V LCD – V LCD +V LCD – V LCD...

  • Page 263

    KS57C2308/P2308/C2316/P2316 Timing Strobe Bit 0 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH Figure 12-12. LCD Connection Example in Static Mode...

  • Page 264

    COM0 COM1 SEG9 COM0– SEG9 COM1– SEG9 Figure 12-13. LCD Signal Waveforms at 1/2 Duty, 1/2 Bias 12-16 KS57C2308/P2308/C2316/P2316 V LC0 V LC1, 2 V SS V LC0 V LC1, 2 V SS V LC0 V LC1, 2 V SS...

  • Page 265

    KS57C2308/P2308/C2316/P2316 Timing Strobe Bit 0 Bit 1 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH Figure 12-14. LCD Connection Example at 1/2 Duty, 1/2 Bias...

  • Page 266

    SEG12 COM0– SEG12 COM1– SEG12 COM2– SEG12 Figure 12-15. LCD Signal Waveforms at 1/3 Duty, 1/2 Bias 12-18 KS57C2308/P2308/C2316/P2316 V LC0 V LC1, 2 V SS V LC0 V LC1, 2 V SS V LC0 V LC1, 2 V SS...

  • Page 267

    KS57C2308/P2308/C2316/P2316 Timing Strobe Bit 0 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH Figure 12-16. LCD Connection Example at 1/3 Duty, 1/2 Bias...

  • Page 268

    COM2 SEG12 COM0– SEG12 COM1– SEG12 COM2– SEG12 Figure 12-17. LCD Signal Waveforms at 1/3 Duty, 1/3 Bias 12-20 KS57C2308/P2308/C2316/P2316 V LC1 V LC2 V LC1 V LC2 V LC1 V LC2 V LC1 V LC2 + V LCD + 1/3 V LCD –...

  • Page 269

    KS57C2308/P2308/C2316/P2316 Timing Strobe Bit 0 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH Figure 12-18. LCD Connection Example at 1/3 Duty, 1/3 Bias...

  • Page 270

    COM1 COM2 COM3 SEG13 COM0– SEG13 COM1– SEG13 Figure 12-19. LCD Signal Waveforms at 1/4 Duty, 1/3 Bias 12-22 KS57C2308/P2308/C2316/P2316 V LC1 V LC2 V LC1 V LC1 V LC2 V LC1 V LC2 V LC1 V LC2 + V LCD + 1/3 V LCD –...

  • Page 271

    KS57C2308/P2308/C2316/P2316 Timing Strobe Bit 0 Bit 1 Bit 2 Bit 3 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH...

  • Page 272

    LCD CONTROLLER/DRIVER KS57C2308/P2308/C2316/P2316 NOTES 12-24...

  • Page 273

    KS57C2308/P2308/C2316/P2316 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW The serial I/O interface (SIO) has the following functional components: — 8-bit mode register (SMOD) — Clock selector circuit — 8-bit buffer register (SBUF) — 3-bit serial clock counter Using the serial I/O interface, 8-bit data can be exchanged with an external device. The transmission frequency is controlled by making the appropriate bit settings to the SMOD register.

  • Page 274

    SELECTOR fxx/2 fxx/2 SMOD.7 SMOD.6 SMOD.5 * Instruction Execution fxx: System Clock 13-2 INTERNAL BUS SBUF (8-BIT) SMOD.3 SMOD.2 SMOD.1 INTERNAL BUS Figure 13-1. Serial I/O Interface Circuit Diagram KS57C2308/P2308/C2316/P2316 LSB or MSB first OVERFLOW 3-BIT COUNTER CLEAR SMOD.0 BITS*...

  • Page 275

    KS57C2308/P2308/C2316/P2316 SERIAL I/O MODE REGISTER (SMOD) The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface. Its reset value is logical zero. SMOD is organized in two 4-bit registers, as follows: FE0H SMOD.3...

  • Page 276

    SERIAL I/O INTERFACE SERIAL I/O TIMING DIAGRAMS IRQS SET SMOD.3 Figure 13-2. SIO Timing in Transmit/Receive Mode IRQS SET SMOD.3 13-4 HIGH IMPEDANCE Figure 13-3. SIO Timing in Receive-Only Mode KS57C2308/P2308/C2316/P2316 TRANSMIT COMPLETE TRANSMIT COMPLETE...

  • Page 277

    KS57C2308/P2308/C2316/P2316 SERIAL I/O BUFFER REGISTER (SBUF) The serial I/O buffer register, SBUF, can be read or written using 8-bit RAM control instructions. Following a , the value of SBUF is undetermined. RESET When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer register are output to the SO pin (P0.2) at the rate of one bit for each falling edge of the SIO clock.

  • Page 278

    ; Store SMB, SRB ; Store EA ; EA (20H–7FH) ; Transmit data ; RDATA address = BANK0 (20H–7FH) ; SIO start / P0.1 SO / P0.2 SI / P0.3 KS57C2308/C2316 KS57C2308/P2308/C2316/P2316 Transmit data, TDATA address = BANK0 Receive data EXTERNAL DEVICE...

  • Page 279

    KS57C2308/P2308/C2316/P2316 PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued) 4. Transmit and receive Data through SIO interface using an external clock in LSB-first mode: BITR EA,TDATA SBUF,EA EA,#0FH SMOD,EA BITS INTS PUSH PUSH BITR EA,TDATA EA,SBUF RDATA,EA BITS SMOD.3...

  • Page 280

    SERIAL I/O INTERFACE KS57C2308/P2308/C2316/P2316 NOTES 13-8...

  • Page 281: Electrical Data

    KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on KS57C2308/C2316 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics —...

  • Page 282

    , XT and XT = 4.5 V to 5.5 V = – 1 mA = 4.5 V to 5.5 V = – 100 µA KS57C2308/P2308/C2316/P2316 Rating – 0.3 to + 6.5 – 0.3 to V + 0.3 – 0.3 to V + 0.3...

  • Page 283

    KS57C2308/P2308/C2316/P2316 Table 14-2. D.C. Electrical Characteristics (Continued) = – 40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Output low voltage Input high LIH1 leakage All input pins except those specified current below for I...

  • Page 284

    = 3 V ± 10% = 3 V ± 10% = 5 V ± 10% = 5 V ± 10% to I ) do not include current drawn through internal pull-up resistors KS57C2308/P2308/C2316/P2316 0.6 V 0.6 V 0.6 V – 0.4 V 0.4 V...

  • Page 285: Test

    KS57C2308/P2308/C2316/P2316 Table 14-3. Main System Clock Oscillator Characteristics = – 40 C + 85 C, V = 1.8 V to 5.5 V) Oscillator Clock Configuration Ceramic Oscillator Crystal Oscillator External Clock Oscillator NOTES: Oscillation frequency and X Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.

  • Page 286

    (t input frequency data are for oscillator characteristics only. Table 14-5. Input/Output Capacitance Condition f = 1 MHz; Unmeasured pins are returned to V KS57C2308/P2308/C2316/P2316 – 32.768 = 4.5 V to 5.5 V – = 1.8 V to 4.5 V –...

  • Page 287

    KS57C2308/P2308/C2316/P2316 = – 40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Instruction cycle time TCL0 input frequency TCL0 input high, TIH0 TIL0 low width cycle time high, low width SI setup time to...

  • Page 288

    Figure 14-1. Standard Operating Voltage Range Symbol Conditions Normal operation DDDR = 1.8 V DDDR DDDR Normal operation SREL Released by RESET WAIT Released by interrupt KS57C2308/P2308/C2316/P2316 Main OSC. Frequency 6 MHz 4.19 MHz 3 MHz – – – – – – – – Unit µA...

  • Page 289

    KS57C2308/P2308/C2316/P2316 TIMING WAVEFORMS EXECUTION OF STOP INSTRUCTION RESET Figure 14-2. Stop Mode Release Timing When Initiated By EXECUTION OF STOP INSTRUCTION POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request STOP MODE...

  • Page 290

    Figure 14-4. A.C. Timing Measurement Points (Except for X X in XT in 14-10 MEASUREMENT POINTS Figure 14-5. Clock Timing Measurement at X Figure 14-6. Clock Timing Measurement at XT KS57C2308/P2308/C2316/P2316 and XT DD – 0.1 V 0.1 V DD – 0.1 V 0.1 V...

  • Page 291

    KS57C2308/P2308/C2316/P2316 TCL0 RESET INT0, 1, 2, 4 KS0 to KS7 Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts TIL0 Figure 14-7. TCL0 Timing Figure 14-8. Input Timing for INTL 0.8 V DD 0.2 V DD ELECTRICAL DATA TIH0 0.8 V DD 0.2 V DD...

  • Page 292

    ELECTRICAL DATA 14-12 t KCY t KL t SIK INPUT DATA t KSO OUTPUT DATA Figure 14-10. Serial Data Transfer Timing KS57C2308/P2308/C2316/P2316 t KH 0.8 V DD 0.2 V DD t KSI 0.8 V DD 0.2 V DD...

  • Page 293: Mechanical Data

    KS57C2308/P2308/C2316/P2316 MECHANICAL DATA This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram — Pad/pin coordinate data table 0.80 NOTE: Dimensions are in millimeters. Figure 15-1. 80-QFP-1420C Package Dimensions 23.90 ± 0.3 20.00...

  • Page 294

    MECHANICAL DATA KS57C2308/P2308/C2316/P2316 NOTES 15-2...

  • Page 295

    OVERVIEW The KS57P2308/P2316 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C2308/C2316 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data format. The KS57P2308/P2316 is fully compatible with the KS57C2308/C2316, both in function and in pin configuration.

  • Page 296: Reset

    RESET RESET P0.0/INT4 P0.1/ P0.2/SO P0.3/SI P1.0/INT0 Figure 16-1. KS57P2308/P2316 Pin Assignments (80-QFP) 16-2 KS57P2308/KS57P2316 (TOP VIEW) NOTE : The bold pins are used for OTP write. KS57C2308/P2308/C2316/P2316 SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31...

  • Page 297

    Pin Name Pin Name SDAT SCLK (TEST) TEST RESET RESET Table 16-2. Comparison of KS57P2308/P2316 and KS57C2308/C2316 Features Characteristic Program Memory Operating Voltage (V OTP Programming Mode Pin Configuration EPROM Programmability OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the Vpp (TEST) pin of the KS57P2308/P2316, the EPROM programming mode is entered.

  • Page 298

    XT OUT, = 4.5 V to 5.5 V = – 1 mA = 4.5 V to 5.5 V = – 100 µA KS57C2308/P2308/C2316/P2316 Rating – 0.3 to + 6.5 – 0.3 to V + 0.3 – 0.3 to V + 0.3...

  • Page 299

    KS57C2308/P2308/C2316/P2316 Table 16-5. D.C. Electrical Characteristics (Continued) = – 40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Output low voltage Input high LIH1 leakage All input pins except those specified current below for I...

  • Page 300

    = 3 V ± 10% = 3 V ± 10% = 5 V ± 10% = 5 V ± 10% to I ) do not include current drawn through internal pull-up resistors and KS57C2308/P2308/C2316/P2316 0.6 V 0.6 V 0.6 V – 0.2 0.4 V 0.4 V...

  • Page 301

    KS57C2308/P2308/C2316/P2316 Table 16-6. Main System Clock Oscillator Characteristics = – 40 C + 85 C, V = 1.8 V to 5.5 V) Oscillator Clock Configuration Ceramic Oscillator Crystal Oscillator External Clock Oscillator NOTES: Oscillation frequency and X Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.

  • Page 302

    (t input frequency data are for oscillator characteristics only. Table 16-8. Input/Output Capacitance Condition f = 1 MHz; Unmeasured pins are returned to V KS57C2308/P2308/C2316/P2316 – 32.768 = 4.5 V to 5.5 V – = 1.8 V to 4.5 V –...

  • Page 303

    KS57C2308/P2308/C2316/P2316 = – 40 C to + 85 C, V = 1.8 V to 5.5 V) Parameter Symbol Instruction cycle time TCL0 input frequency TCL0 input high, TIH0 TIL0 low width cycle time high, low width SI setup time to...

  • Page 304

    Figure 16-2. Standard Operating Voltage Range Symbol Conditions Normal operation DDDR = 1.8 V DDDR DDDR Normal operation SREL Released by RESET WAIT Released by interrupt KS57C2308/P2308/C2316/P2316 Main OSC. Frequency 6 MHz 4.19 MHz 3 MHz – – – – – – – – Unit µA...

  • Page 305

    KS57C2308/P2308/C2316/P2316 TIMING WAVEFORMS EXECUTION OF STOP INSTRUCTION RESET Figure 16-3. Stop Mode Release Timing When Initiated By EXECUTION OF STOP INSTRUCTION POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) Figure 16-4. Stop Mode Release Timing When Initiated By Interrupt Request STOP MODE...

  • Page 306

    Figure 16-5. A.C. Timing Measurement Points (Except for X X in XT in 16-12 MEASUREMENT POINTS Figure 16-6. Clock Timing Measurement at X Figure 16-7. Clock Timing Measurement at XT KS57C2308/P2308/C2316/P2316 and XT DD – 0.1 V 0.1 V DD – 0.1 V 0.1 V...

  • Page 307

    KS57C2308/P2308/C2316/P2316 TCL0 RESET INT0, 1, 2, 4 KS0 to KS7 Figure 16-10. Input Timing for External Interrupts and Quasi-Interrupts TIL0 Figure 16-8. TCL0 Timing Figure 16-9. Input Timing for INTL 0.8 V DD 0.2 V DD KS57P2308/P2316 OTP TIH0 0.8 V DD 0.2 V DD...

  • Page 308

    KS57P2308/P2316 OTP 16-14 t KCY t KL t SIK INPUT DATA t KSO OUTPUT DATA Figure 16-11. Serial Data Transfer Timing KS57C2308/P2308/C2316/P2316 t KH 0.8 V DD 0.2 V DD t KSI 0.8 V DD 0.2 V DD...

  • Page 309

    KS57C2308/P2308/C2316/P2316 FAIL Verify Byte Device Failed START Address= First Location =5V, V =12.5V x = 0 Program One 1ms Pulse Increment X x = 10 Verify 1 Byte Last Address = 5 V FAIL Compare All Byte PASS Device Passed Figure 16-12.

  • Page 310

    KS57P2308/P2316 OTP KS57C2308/P2308/C2316/P2316 NOTES 16-16...

  • Page 311

    SMDS2+, for KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+.

  • Page 312

    DEVELOPMENT TOOLS IBM-PC AT or Compatible RS-232C Figure 17-1. SMDS Product Configuration (SMDS2+) 17-2 PROM/MTP WRITER UNIT RAM BREAK/ DISPLAY UNIT TRACE/TIMER UNIT SAM4 BASE UNIT POWER SUPPLY UNIT KS57C2308/P2308/C2316/P2316 SMDS2+ TARGET APPLICATION SYSTEM PROBE ADAPTER TB572308A/16A TARGET BOARD CHIP...

  • Page 313

    KS57C2308/P2308/C2316/P2316 TB572308A/16A TARGET BOARD The TB572308A/16A target board is used for the KS57C2308/P2308/C2316/P2316 microcontroller. It is supported by the SMDS2+ development system. To User_Vcc RESET EXTERNAL TRIGGERS Figure 17-2. TB572308A/16A Target Board Configuration TB572308A/16A 74HC11 144 QFP KS57E2308 EVA CHIP...

  • Page 314

    SMDS2/SMDS2+ Operating Mode EVA CHIP KS57E2308 No connection 100 pin connector SMDS2/SMDS2+ EVA CHIP KS57E2308 XTAL TARGET BOARD KS57C2308/P2308/C2316/P2316 Comments The SMDS2/SMDS2+ supplies V to the target TARGET board (evaluation chip) and SYSTEM the target system. The SMDS2/SMDS2+ supplies V...

  • Page 315

    KS57C2308/P2308/C2316/P2316 Table 17-3. Sub-clock Selection Settings for TB572308A/16A Sub Clock Setting XTAL XTAL Table 17-4. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part EXTERNAL TRIGGERS IDLE LED This LED is ON when the evaluation chip (KS57E2308) is in idle mode.

  • Page 316

    P2.3/BUZ P3.1/LCDSY P3.3 P4.1 P4.3 Figure 17-3. 40-Pin Connectors for TB572308A/16A TARGET BOARD J101 J102 39 40 39 40 Figure 17-4. TB572308A/16A Adapter Cable for 80-QFP Package (KS57C2308/P2308/C2316/P2316) 17-6 SEG1 COM0 COM2 P6.1/KS1 BIAS P6.3/KS3 P7.1/KS5 P7.3/KS7 X OUT P8.6/SEG30 TEST P8.4/SEG28...

  • Page 317

    New product Replacement of an existing product If you are replacing an existing product, please indicate the former product name What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price...

  • Page 319

    _______________________________ (Person Placing the Risk Order) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) KS57 SERIES ________________________________________________________________ ________________________________________________________________...

  • Page 321

    Please describe in detail its application ___________________________________________________________________________ (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) KS57C2308-__________(write down the ROM code number) Diskette...

  • Page 323

    Please describe in detail its application ___________________________________________________________________________ (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) KS57C2316-__________(write down the ROM code number) Diskette...

  • Page 324

    New product development Replacement of an existing microcontroller If you are replacing an existing microcontroller, please indicate the former microcontroller name What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price...

  • Page 326

    Once you choose a read protection, you cannot read again the programming code from the EPROM. OTP writing will be executed in our manufacturing site. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.

  • Page 328

    Once you choose a read protection, you cannot read again the programming code from the EPROM. OTP writing will be executed in our manufacturing site. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.

This manual also for:

P2308, C2316, P2316, Ks57p2308, Ks57c2316, Ks57p2316

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