Table of Contents
Advertisement
4. The ADST bit is not cleared automatically, and steps 2 and 3 are repeated as long as the ADST
bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D
converter enters the wait state. Then if the ADST bit is set to 1, A/D conversion starts again for
the first channel in the channel set.
18.4.3
Input Sampling and A/D Conversion Time
The A/D converter has an on-chip sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
then starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As shown in figure 18.2, the A/D conversion time (t
(t
). The length of t
SPL
D
conversion time therefore varies within the ranges indicated in tables 18.3.
In scan mode, the values given in tables 18.3 apply to the first conversion time. The values given
in table 18.4 apply to the second and subsequent conversions.
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
(2):
t
:
D
t
:
SPL
t
CONV
varies depending on the timing of the write access to ADCSR. The total
(1)
(2)
t
D
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
A/D conversion time
:
Figure 18.2 A/D Conversion Timing
) passes after the ADST bit in ADCSR is set to 1,
D
) includes t
CONV
t
SPL
t
CONV
Rev. 1.00, 09/03, page 515 of 704
and the input sampling time
D
Advertisement
Table of Contents
