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16.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 16.3 shows the A/D conversion timing. Table 16.3 indicates
the A/D conversion time.
As indicated in figure 16.3, the A/D conversion time (t
(t
). The length of t
SPL
D
conversion time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states
(fixed) when CKS = 1.
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
ADCSR write cycle
(2):
ADCSR address
t
:
A/D conversion start delay
D
t
:
Input sampling time
SPL
t
: A/D conversion time
CONV
varies depending on the timing of the write access to ADCSR. The total
(1)
(2)
t
t
D
SPL
Figure 16.3 A/D Conversion Timing
) passes after the ADST bit in ADCSR is set to
D
) includes t
CONV
D
t
CONV
Rev. 1.00, 05/04, page 421 of 544
and the input sampling time
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