Slave Address Register (Sar) - Renesas H8S/2111B Hardware Manual

13.3.2

Slave Address Register (SAR)

SAR sets the slave address and selects the communication format. If the LSI is in slave mode with
2
the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared
to 0.
Bit Bit Name Initial Value R/W
7 SVA6 0
6 SVA5 0
5 SVA4 0
4 SVA3 0
3 SVA2 0
2 SVA1 0
1 SVA0 0
0 FS 0
Description
R/W Slave Address 6 to 0
R/W Set a slave address.
R/W
R/W
R/W
R/W
R/W
R/W Format Select
Selects the communication format together with the FSX bit
in SARX. See table 13.2.
This bit should be set to 0 when general call address
recognition is performed.
Rev. 1.00, 05/04, page 283 of 544