Timer Mode Register (Tmdr) - Renesas H8S/2100 Series Hardware Manual

10.3.2

Timer Mode Register (TMDR)

The TMDR registers are used to set the operating mode for each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit Bit Name

7

6
5 BFB
4 BFA
3 MD3
2 MD2
1 MD1
0 MD0
Initial
value R/W Description
1 R Reserved
1 R These bits are always read as 1 and cannot be
modified.
0 R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register. TGRD input capture/output compare is not
generation. Because channels 1 and 2 have no TGRD,
bit 5 is reserved. It is always read as 0 and cannot be
modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
0 R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated. Because channels 1 and 2 have no TGRC,
bit 4 is reserved. It is always read as 0 and cannot be
modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
0 R/W Modes 3 to 0
0 R/W These bits are used to set the timer operating mode.
0 R/W MD3 is a reserved bit. In a write, the write value should
always be 0. See table 10.9 for details.
0 R/W
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 1.00 Apr. 28, 2008 Page 247 of 994
REJ09B0452-0100