Timer Mode Register (Tmdr) - Renesas F-ZTAT H8 Series Hardware Manual

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.3

Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit 7
—
Initial value 1
Read/Write —
Reserved bit
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6: MDF Description
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
Rev. 7.00 Sep 21, 2005 page 330 of 878
REJ09B0259-0700
6 5
MDF FDIR PWM4
0 0
R/W R/W
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
4 3 2
PWM3 PWM2
0 0 0
R/W R/W R/W
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
1 0
PWM1 PWM0
0 0
R/W R/W
(Initial value)