Figure 7.2 Areas For Register Re-Setting By Dtc (Channel 0A) - Renesas H8S/2368 Series Hardware Manual

Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)

Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
Rev. 2.00, 05/03, page 224 of 820
First transfer area
DTC
Second transfer area
using chain transfer
MAR_0A
IOAR_0A
ETCR_0A
MAR_0B
IOAR_0B
ETCR_0B
MAR_1A
IOAR_1A
ETCR_1A
MAR_1B
IOAR_1B
ETCR_1B
DMAWER DMATCR
DMACR_0A DMACR_0B
DMACR_1A DMACR_1B
DMABCR