Figure 18.74 Conflict Between Buffer Register Write And Compare Match (Channel 0); Figure 18.75 Conflict Between Buffer Register Write And Compare Match (Channels 3 And 4); Channels 3 And - Renesas HD6417641 Hardware Manual

Pφ
Address
Write signal
Compare
match signal
Compare
match buffer
signal
Buffer register
TGR

Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0)

Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR
Figure 18.75 Conflict between Buffer Register Write and Compare Match
Section 18 Multi-Function Timer Pulse Unit (MTU)
TGR write cycle
T1 T2
Buffer register
address
N
TGR write cycle
T1
T2
Buffer register
address
N

(Channels 3 and 4)

Buffer register write data
M
M
Buffer register write data
M
N
Rev. 4.00 Sep. 14, 2005 Page 631 of 982
REJ09B0023-0400