Register Configuration; Register Descriptions; Timer Counter (Tcnt) - Renesas F-ZTAT H8 Series Hardware Manual

12.1.4

Register Configuration

Table 12.2 summarizes the WDT registers.
Table 12.2 WDT Registers
1
Address *
2
Write *
Read
H'FFA8 H'FFA8
H'FFA9
H'FFAA H'FFAB
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
12.2

Register Descriptions

12.2.1

Timer Counter (TCNT)

TCNT is an 8-bit readable and writable* up-counter.
Bit 7
Initial value 0
Read/Write R/W
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register
Access.
Name
Timer control/status register
Timer counter
Reset control/status register
6 5
0 0
R/W R/W
Section 12 Watchdog Timer
Abbre-
viation
TCSR
TCNT
RSTCSR
4 3 2
0 0 0
R/W R/W R/W
Rev. 7.00 Sep 21, 2005 page 439 of 878
Initial
R/W Value
3
R/(W) *
H'18
R/W H'00
3
R/(W) *
H'3F
1 0
0 0
R/W R/W
REJ09B0259-0700