Chip Select Control Register (Csr) - Renesas M16C/64C User Manual

M16C/64C Group
11.2.1

Chip Select Control Register (CSR)

Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1
CSiW (CSi wait bit) (i = 0 to 3) (b7-b4)
Set the CSiW bit to 0 (wait state) under the following conditions:
The RDY signal is used in the area indicated by CSi .
•
The multiplexed bus is used in the area indicated by CSi .
•
•
The PM17 bit in the PM1 register is 1 (wait state) in memory expansion mode or microprocessor
mode.
When the CSiW bit is 0 (wait state), the number of wait states can be selected using bits CSEi1W to
CSEi0W in the CSE register.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
b0
Symbol
CSR
Bit Symbol Bit Name
CS0 output enable bit
CS0
CS1 CS1 output enable bit
CS2 CS2 output enable bit
CS3 CS3 output enable bit
CS0W CS0 wait bit
CS1W CS1 wait bit
CS2W CS2 wait bit
CS3W CS3 wait bit
Address
0008h
0 : Chip select output disabled
(functions as an I/O port)
1 : Chip select output enabled
0 : Wait state
1 : No wait state
Reset Value
01h
Function
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11. Bus
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