Fig. 2.8.4 I C Clock Control Register - Renesas 7200 Series User Manual

FUNCTIONAL DESCRIPTION
2.8 Multi-master I
2
I C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
2
Fig. 2.8.4 I C clock control register
2-52
2 C-BUS interface
I 2 C clock control register (S2 : address 00DB
B
0
SCL frequency control bits
to
(CCR0 to CCR4)
4
5 SCL mode
specification bit
(FAST MODE)
6 ACK bit
(ACK BIT)
7 ACK clock bit
(ACK)
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
"0" period : "1" period = 3 : 2
In the other cases, the duty is as below.
"0" period : "1" period = 1 : 1
7220 Group User's Manual
16
Name
Setup value of Standard clock
CCR4–CCR0
00 to 02
Setup disabled Setup disabled
03 Setup disabled
04
Setup disabled
05
06
500/CCR value
1D
1E
1F
(at φ = 4 MHz, unit : kHz)
0 : Standard clock mode
1 : High-speed clock mode
0 : ACK is returned.
1 : ACK is not returned.
0 : No ACK clock
1 : ACK clock
)
Functions After reset R W
High speed
0
mode clock mode
333
250
100 400 (See note)
83.3 166
1000/CCR value
17.2 34.5
16.6 33.3
16.1
32.3
0
0
0
R W
R W
R W
R W