Internal Clock; Figure 12.23 Pin States During Transmission In Clocked Synchronous Mode; Figure 12.24 Sample Flowchart For Mode Transition During Reception - Renesas H8S/2111B Hardware Manual

TE bit
SCK
output pin
TxD
Port
input/output
output pin
Port
Note: * Initialized in software standby mode

Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode

Read RDRF flag in SSR
Read receive data in RDR
Make transition to software
standby mode etc.
Cancel software standby mode etc.
Change operating mode?

Figure 12.24 Sample Flowchart for Mode Transition during Reception

Transmission start
Marking output
SCI TxD output

(Internal Clock)

Reception
No
RDRF = 1
Yes
RE = 0
No
Yes
Initialization
Start reception
Transmission end
Last TxD bit retained
[1]
[1] Data being received will be invalid.
[2] Module stop, watch, sub-active, and
sub-sleep modes are included
[2]
RE = 1
Rev. 1.00, 05/04, page 275 of 544
Transition to
Software standby
software standby
mode cancelled
mode
Port
input/output
Port input/output
Port
High output*
SCI
TxD output