Figure 14.36 Pin States During Transmission In Clocked Synchronous Mode - Renesas H8S Series Hardware Manual

TE bit
SCK
output pin
TxD
Port
input/output
output pin
Port
Note: * Initialized in software standby mode

Figure 14.36 Pin States during Transmission in Clocked Synchronous Mode

Reception: Before making the transition to module stop, software standby, watch, sub-active, or
sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 14.37 shows a sample flowchart for mode transition during reception.
Transmission start
Marking output
SCI TxD output
(Internal Clock)
Section 14 Serial Communication Interface (SCI)
Transition to
Transmission end software standby
mode
Port input/output
Last TxD bit retained
Rev. 6.00 Mar 15, 2006 page 381 of 570
Software standby
mode cancelled
Port
input/output
High output *
SCI
Port
TxD output
REJ09B0211-0600