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TE bit
SCK
output pin
TxD
Port
input/output
output pin
Port
Figure 16.22 Pin States during Transmission in Asynchronous Mode (Internal Clock)
TE bit
SCK
output pin
TxD
Port
input/output
output pin
Port
Note: * Initialized in software standby mode
Figure 16.23 Pin States during Transmission in Clocked Synchronous Mode
Reception: Before making the transition to module stop, software standby, watch, subactive, or
subsleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 16.24 shows a sample flowchart for mode transition during reception.
Transmission start
High output
Start
SCI TxD output
Transmission start
Marking output
SCI TxD output
(Internal Clock)
Transition to
software standby
Transmission end
mode
Stop
Transition to
Transmission end
software standby
mode
Last TxD bit retained
Rev. 1.00, 09/03, page 471 of 704
Software standby
mode cancelled
Port
input/output
Port input/output
High output
SCI
Port
TxD output
Software standby
mode cancelled
Port
input/output
Port input/output
High output*
SCI
Port
TxD output
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