Operation; Transmission In Clock-Synchronous Serial I/O Mode - Renesas M16C Series User Manual

16-bit single-chip microcomputer
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2.4.2 Operation

2.4.2.1 Transmission in clock-synchronous serial I/O mode

In transmitting data in clock-synchronous serial I/O mode, select functions from those listed in Table
2.14. An example using the indicated options is described below. Figure 2.46 shows the operation
timing, and Figures 2.47 and 2.48 show the set-up procedures.
Table 2.14:
Serial I/O transmission in clock synchronous serial I/O mode functions
Item
O
Transfer clock source
O
CTS function
O
CLK polarity
O
Transfer clock
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
selected, the CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disabled bit to "0".
Note 2: UART2 only.
Operation
(1) Setting the transmit enable bit to "1" and writing transmission data to the UARTi transmit butter reg-
ister makes data transmission status ready.
(2) When the input to the CTSi pin goes to "L" level, transmission starts (the CTSi pin must be con-
trolled on the reception side).
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the UARTi
transmit interrupt request bit goes to "1". Also, the first bit of the transmission data is transmitted from
the TxDi pin. Then the data is transmitted bit by bit from the lower order in synchronization with the
falling edges.
(4) When transmission of 1-byte of data is completed, the transmit register empty flag goes to "1",
which indicates that transmission is completed. The transfer clock stops at "H" level.
(5) If the next transmission data is set in the UARTi transmit buffer register while a transmission is in
progress (before the eighth bit has been transmitted), the data is transmitted in succession.
Rev.1.00 Sep 24, 2003 Page 186 of 360
Set-up
Internal clock (f1/f8/f32)
External clock (CLKi pin)
CTS function enabled
CTS function disabled
Output transmission data at the
falling edge of the transfer clock
Output transmission data at the
rising edge of the transfer clock
LSB first
MSB first
Clock-Synchronous Serial I/O
Item
O
Transmission interrupt
factor
O
Output transfer clock to
multiple pins (Note 1)
O
Data logic select function
(Note 2)
O
TxD, RxD I/O polarity
reverse bit (Note 2)
Set-up
Transmission buffer empty
Transmission complete
Not selected
Selected
No reverse
Reverse
No reverse
Reverse

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