Operations; Common Specifications Between The Internal Bus And External Bus - Renesas M16C/64C User Manual

M16C/64C Group
11.3

Operations

11.3.1

Common Specifications between the Internal Bus and External Bus

11.3.1.1 Reference Clock
Both the internal and external buses operate based on the BCLK. However, the area accessed and
wait states affect bus operation. Refer to 11.3.2.1 "Software Wait States of the Internal Bus" and
11.3.5.9 "Software Wait States" for details.
11.3.1.2 Bus Hold
Both the internal and external buses are in a hold state under the following condition:
•
Rewriting the flash memory in EW1 mode while auto-programming or auto-erasing
When the bus is in hold state, the following occur:
•
CPU stops
•
DMAC stops
•
The watchdog timer stops when the CSPRO bit in the CSPR register is 0 (count source protection
mode disabled)
•
State of I/O ports is retained.
Bus use priority is given to bus hold, DMAC, and CPU in descending order. However, if the CPU is
accessing an odd address in word units, DMAC cannot gain control of the bus between two separate
accesses.
Figure 11.1 Bus Use Priority
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Bus Hold > DMAC > CPU
11. Bus
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