External Bus Status When Internal Area Accessed; Software Wait - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

(9) External Bus Status When Internal Area Accessed

Table 1.7.6 shows the external bus status when the internal area is accessed.
Table 1.7.6 External Bus Status When Internal Area Accessed
Item
A to A
0 19
D to D When read High-impedance
0 15
When write Output data
_____ ______ ________ _________
RD, WR, WRL, WRH
________
BHE
_______ _______
CS to CS
0 3
ALE

(10) Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. Refer
to "Table 1.7.7 Bit and Bus Cycle Related to Software Wait " for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to "0" (with wait state). Figure 1.7.6
shows the CSE register. Table 1.7.7 shows the software wait related bits and bus cycles. Figures 1.7.7
and 1.7.8 show the typical bus timings using software wait.
Chip select expansion control register
b7 b6 b5 b4 b3 b2
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to CSEi0W
bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to "00
setting it.
Figure 1.7.6 CSE Register
Rev.1.00 2003.05.30 page 38
SFR accessed
Address output
_____ ______ _________ __________
RD, WR, WRL, WRH output
________
BHE output
Output "H"
Output "L"
b1 b0
Symbol Address
CSE 001B
Bit symbol
CSE00W
wait expansion bit
CS
0
CSE01W
CSE10W
wait expansion bit
CS
1
CSE11W
CSE20W
wait expansion bit
CS
2
CSE21W
CSE30W
wait expansion bit
CS
3
CSE31W
Internal ROM, internal RAM accessed
Maintain status before accessed address
of external area or SFR
High-impedance
Undefined
Output "H"
Maintain status before accessed status of
external area or SFR
Output "H"
Output "L"
After reset
00
16 16
Bit name
b1 b0
0 0 : 1 wait
0 1 : 2 waits
(Note)
1 0 : 3 waits
1 1 : Must not be set
b3 b2
0 0 : 1 wait
0 1 : 2 waits
(Note) 1 0 : 3 waits
1 1 : Must not be set
b5 b4
0 0 : 1 wait
0 1 : 2 waits
(Note)
1 0 : 3 waits
1 1 : Must not be set
b7 b6
0 0 : 1 wait
0 1 : 2 waits
(Note)
1 0 : 3 waits
1 1 : Must not be set
Bus Control
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
" before
2