Timer General Register (Tgr); Timer Start Register (Tstr) - Renesas H8S/2368 Series Hardware Manual

The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.3.7

Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers with a dual function as output compare
and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two
each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for
operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must
always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and
TGRB–TGRD.
10.3.8

Timer Start Register (TSTR)

TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit Bit Name Initial value
–
7 0
–
6 0
5 CST5 0
4 CST4 0
3 CST3 0
2 CST2 0
1 CST1 0
0 CST0 0
R/W Description
–
Reserved
–
The write value should always be 0.
R/W Counter Start 5 to 0
R/W
These bits select operation or stoppage for TCNT.
R/W
If 0 is written to the CST bit during operation with the
R/W
TIOC pin designated for output, the counter stops but
R/W
the TIOC pin output compare output level is retained.
R/W
If TIOR is written to when the CST bit is cleared to 0,
the pin output level will be changed to the set initial
output value.
0: TCNT_5 to TCNT_0 count operation is stopped
1: TCNT_5 to TCNT_0 performs count operation
Rev. 2.00, 05/03, page 409 of 820