Refresh Timer Control/Status Register (Rtcsr) - Renesas HD6417641 Hardware Manual

Bit Bit Name

2
1 A3COL1
0 A3COL0
12.4.5

Refresh Timer Control/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM. This register is initialized to
H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby
mode. When the RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel
write protection.
The clock which counts up the refresh timer counter (RTCNT) is adjusted its phase only by a
power-on reset. Thus, when CKS[2:0] are set to other than B'000 and a timer is in operation, an
error is found until the first compare match flag is set.
Bit Bit Name

31 to 8
7 CMF
Initial
Value R/W Description
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
0 R/W Number of Bits of Column Address for Area 3
0 R/W Specify the number of bits of the column address for
area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (Setting prohibited)
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0.
0 R/W Compare Match Flag
Indicates that a compare match occurs between the
refresh timer counter (RTCNT) and refresh time
constant register (RTCOR). This bit is set or cleared in
the following conditions.
0: Clearing condition: When 0 is written in CMF after
1: Setting condition: When the condition RTCNT =
Section 12 Bus State Controller (BSC)
reading out RTCSR during CMF = 1.
RTCOR is satisfied.
Rev. 4.00 Sep. 14, 2005 Page 317 of 982
REJ09B0023-0400