Basic Instruction Formats; Figure 2.14 Instruction Formats - Renesas H8SX/1500 Series Hardware Manual

2.7.3

Basic Instruction Formats

The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.14 shows examples of instruction formats.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
op
• Operation Field
Indicates the function of the instruction, and specifies the addressing mode and operation to be
carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branch condition of Bcc instructions.
op
op
rn
op
EA (disp)
cc

Figure 2.14 Instruction Formats

NOP, RTS, etc.
rm
ADD.B Rn, Rm, etc.
rn rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp) BRA d:16, etc
Rev. 3.00 Mar. 14, 2006 Page 53 of 804
Section 2 CPU
REJ09B0104-0300