Pwm Modes - Renesas H8SX/1500 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.5

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
(1)
PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are
output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs
specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and
D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of
paired TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
Rev. 3.00 Mar. 14, 2006 Page 313 of 804
REJ09B0104-0300