Figure 5.3 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control - Renesas H8S Series Hardware Manual

Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
Rev. 6.00 Mar 15, 2006 page 80 of 570
REJ09B0211-0600
Program execution status
Interrupt generated?
Yes
NMI
I = 0
No
IRQ0
Yes
IRQ1
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
in Interrupt Control Mode 0
No
Yes
No
No
Yes
No
Yes
TEI_2
Yes
Hold
pending