Timer Buffer Registers (Tbr); Timer General Registers (Tgr); Timer Dead Time Counters (Tdcnt); Timer Dead Time Data Register (Tddr) - Renesas H8S Series Hardware Manual
16-bit single-chip microcomputer
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11.3.5
Timer Buffer Registers (TBR)
The timer buffer registers (TBR) function as 16-bit buffer registers. The MMT has three TBR
registers; TBRU, TBRV, and TBRW, each of which have two addresses; a buffer operation
address (shown first) and a free operation address (shown second). A value written to the buffer
operation address is transferred to the corresponding TGR at the timing set in bits MD1 and MD0
in the timer mode register (TMDR). A value set in the free operation address is transferred to the
corresponding TGR immediately. Only 16-bit access can be used on the TBR registers; 8-bit
access is not possible.
11.3.6
Timer General Registers (TGR)
The timer general registers (TGR) function as 16-bit compare registers. The MMT has nine TGR
registers, that are compared with the TCNT counter in the operating modes. Only 16-bit access
can be used on the TGR registers; 8-bit access is not possible.
11.3.7
Timer Dead Time Counters (TDCNT)
The timer dead time counters (TDCNT) are 16-bit read-only counters. Only 16-bit access can be
used on the TDCNT counters; 8-bit access is not possible.
11.3.8
Timer Dead Time Data Register (TDDR)
The timer dead time data register (TDDR) is a 16-bit register that sets the positive phase and
negative phase non-overlap time (dead time). Only 16-bit access can be used on TDDR; 8-bit
access is not possible.
11.3.9
Timer Period Buffer Register (TPBR)
The timer period buffer register (TPBR) is a 16-bit register that functions as a buffer register for
the TPDR register. A value of 1/2 the PWM carrier period should be set as the TPBR value. The
TPBR value is transferred to the TPDR register at the transfer timing set in the TMDR register.
Only 16-bit access can be used on TPBR; 8-bit access is not possible.
11.3.10 Timer Period Data Register (TPDR)
The timer period data register (TPDR) functions as a 16-bit compare register. In the operating
modes, the TPDR register value is constantly compared with the TCNT counter value, and when
Section 11 Motor Management Timer (MMT)
Rev. 6.00 Mar 15, 2006 page 251 of 570
REJ09B0211-0600
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