I 2 C0 Start/Stop Condition Control Registers (S2D0 Register); Bit0-Bit4: Start/Stop Condition Setting Bits (Ssc0-Ssc4); Bit5: Scl/Sda Interrupt Pin Polarity Select Bit (Sip); Bit6 : Scl/Sda Interrupt Pin Select Bit (Sis) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
2
16.8 I C0 START/STOP condition control registers (S2D0 register)
2
The I C0 START/STOP condition control register(address 02E5
STOP condition.

16.8.1 Bit0-Bit4: START/STOP condition setting bits (SSC0-SSC4)

Because the release time, the set up time and the hold time of the S
bus system clock(V
2
the I C bus system clock select bits. It is necessary to set the appropriate value of START/STOP condition
setting bits (SSC4-SSC0) and set the release time, the set up time and the hold time by the system clock
frequency. Refer to Table 16.10 Start/Stop condition detect conditions. Do not set odd numbers or
"00000 " to START/STOP condition setting bits. Table 16.2 shows the recommended setting value to START/
2
STOP condition setting bits (SSC4-SSC0) at each oscillation frequency under standard clock mode. The
detection of the START/STOP condition starts immediately after setting the ES0 bit to "1".
16.8.2 Bit5: S
CL
The S /S interrupt can be generated by detecting the rising edge or the falling edge of the S
CL DA
the S pin. The S
DA
interrupt.
16.8.3 Bit6 : S
The S /S interrupt pin select bit selects either the S
CL DA
pin.
NOTES:
The S /S interrupt request may be set when the setting of the S
CL DA
bit, S /S interrupt pin select bit and I
CL DA
S /S interrupt, write "0" to the S
CL DA
the S /S interrupt.
CL DA

16.8.4 Bit7: START/STOP condition generation select bit (STSPSEL)

The bit selects the length of the set up and the hold time when the START/STOP condition is generated. The
length of the set up and hold time is based on the I
generation timing table. Set the bit to "1" if the I
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
). The detecting condition changes depending on the oscillation frequency (X
IIC
/S interrupt pin polarity select bit (SIP)
DA
/S interrupt pin polarity select bit selects the polarity of the S
CL DA
/S interrupt pin select bit (SIS)
CL DA
/S
CL
page 269 of 402
pin or the S
CL
2
C bus interface enable bit ES0 are changed. When using the
interrupt request bit after setting the above bits, and enable
DA
2
C system clock cycles. Refer to Table 16.8 Start/Stop
2
C bus system clock frequency is over 4MHz.
2
16. MULTI-MASTER I C bus INTERFACE
) controls the detection of the START/
16
are measured on the base of the I
CL
pin or the S
CL
pin as the S /S
DA CL
/S interrupt pin polarity se lect
CL DA
2
C
) and
IN
pin or
CL
pin for
DA
interrupt enable
DA