Interrupt Sources And Dma Controller Activation - Renesas F-ZTAT H8 Series Hardware Manual

16-bit single-chip microcomputer

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Section 10 16-Bit Integrated Timer Unit (ITU)

Interrupt Sources and DMA Controller Activation

Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input

capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all

independently vectored. An interrupt is requested when the interrupt request flag and interrupt

enable bit are both set to 1.

The priority order of the channels can be modified in interrupt priority registers A and B (IPRA

and IPRB). For details see section 5, Interrupt Controller.

Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller

(DMAC). When the DMAC is activated a CPU interrupt is not requested.

Table 10.10 lists the interrupt sources.

Table 10.10 ITU Interrupt Sources

Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed

by settings in IPRA and IPRB.

Rev. 7.00 Sep 21, 2005 page 394 of 878

REJ09B0259-0700

Compare match/input capture A0

Compare match/input capture B0

Compare match/input capture A1

Compare match/input capture B1

Compare match/input capture A2

Compare match/input capture B2

Compare match/input capture A3

Compare match/input capture B3

Compare match/input capture A4

Compare match/input capture B4

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