Address Register (Lr2) - Renesas F-ZTAT H8 Series Hardware Manual

13.2.4

Address Register (LR2)

Bit
7
XA2
Initial value
0
Read/Write
W
LR2 is an 8-bit write-only register that sets the display memory X- and Y-direction addresses
accessed by the CPU.
Upon reset, LR2 is initialized to H'00.
Bits 7 to 5—X Address Setting (XA2 to XA0): Bits 7 to 5 set the display memory X-direction
address. A value from H'0 to H'7 can be set, but if the SOB bit in LR0 is set to 1, display data H'7
is invalid with 1/16 duty, and display data from H'5 to H'7 is invalid with 1/32 duty.
When the INC bit in LR1 is set to 1, the address is automatically incremented after the access
specified by the RMW bit in LR1, and is cleared after an access with the maximum value for the
valid display data area. When INC is 0 and YA4 to YA0 represent the maximum value for the
valid display data area, the address is incremented after the access specified by RMW.
Bits 4 to 0—Y Address Setting (YA4 to YA0): Bits 4 to 0 set the display memory Y-direction
address. A value from H'00 to H'1F can be set, but display data from H'10 to H'1F is invalid with
1/16 duty, and display data from H'08 to H'1F is invalid with 1/8 duty.
When the INC bit in LR1 is cleared to 0, the address is automatically incremented after the access
specified by the RMW bit in LR1, and is cleared after an access with the maximum value for the
valid display data area. When INC is 1 and XA2 to XA0 represent the maximum value for the
valid display data area, the address is incremented after the access specified by RMW.
6 5
XA1 XA0 YA4
0 0
W W
13. Dot Matrix LCD Controller (H8/3857 Group)
4 3
YA3 YA2
0 0
W W W
Rev.3.00 Jul. 19, 2007 page 335 of 532
2 1
YA1 YA0
0 0
W W
REJ09B0397-0300
0
0