Fig. 2.8.3 I C Address Register - Renesas 7200 Series User Manual

FUNCTIONAL DESCRIPTION
2.8 Multi-master I
2
(2) I C address register (S0D: address 00D8
2
The I C address register (address 00D8
the addressing mode, the slave address written in this register is compared with the address data
to be received immediately after the START condition are detected.
Bit 0: Read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the
I 2 C address register.
The RBW bit is cleared to "0" automatically when the stop condition is detected.
Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
Figure 2.8.3 shows the I
2
I C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
2
Fig. 2.8.3 I C address register
2-50
2 C-BUS interface
2 C address register.
2
I C address register (S0D) [Address 00D8
B
0
Read/write bit
(RBW)
1
Slave address
to
(SAD0 to SAD6)
7
7220 Group User's Manual
)
16
) consists of a 7-bit slave address and a read/write bit. In
16
Name
0: Read
1: Write
The address data transmitted from
the master is compared with the
contents of these bits.
]
16
Functions After reset R W
0
0
R W
R W