Register Descriptions; Break Address Register A (Bara); Figure 6.1 Block Diagram Of Pc Break Controller - Renesas H8S Series Hardware Manual

Section 6 PC Break Controller (PBC)
Internal address
Access
status
6.2

Register Descriptions

The PC break controller has the following registers. For details on register addresses and register
states during each process, refer to appendix A, On-Chip I/O Register.

• Break address register A (BARA)

• Break address register B (BARB)
• Break control register A (BCRA)
• Break control register B (BCRB)
6.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register that specifies the channel A break address.
Bit Bit Name
31 to 24 —
23 to 0 BAA23 to BAA0
Rev. 6.00 Mar 15, 2006 page 90 of 570
REJ09B0211-0600
BARA
Mask control
Comparator
Match signal
Comparator
Match signal
Mask control
BARB

Figure 6.1 Block Diagram of PC Break Controller

Initial Value
Undefined
H'000000
BCRA
Control
logic
Control
logic
BCRB
R/W Description
— Reserved
These bits are read as an undefined value
and cannot be modified.
R/W These bits set the channel A PC break
address.
PC break
interrupt