Clock Phase Setting Function; Master (Internal Clock); Slave (External Clock) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

14.1.4.1 Clock Phase Setting Function

One of four combinations of transfer clock phases and polarities can be selected using the U2SMR3
register's CKPH bit and the U2C0 register's CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and slave to communi-
cate.

14.1.4.1.1 Master (Internal Clock)

Figure 14.1.4.1.1.1 shows the transmission and reception timing in master (internal clock).

14.1.4.1.2 Slave (External Clock)

Figure 14.1.4.1.2.1 shows the transmission and reception timing (CKPH=0) in slave (external clock)
while Figure 14.1.4.1.2.2 shows the transmission and reception timing (CKPH=1) in slave (external
clock).
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
Clock output
(CKPOL=1, CKPH=1)
Data output timing
Data input timing
Figure 14.1.4.1.1.1. Transmission and Reception Timing in Master Mode (Internal Clock)
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D
0
"L"
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14.1.4 Special Mode 2 (UART2)
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