Stop Mode; Wait Mode; Status Transition Of Internal Clock Φ - Renesas M16C Series User Manual

M30240 Group

1.2.7 Stop Mode

Writing "1" to the all-clock stop control bit (bit 0 at address 0007
microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided
that V remains above 2V.
CC
Because the oscillation of internal clock Φ, f
such as the A-D converter and watchdog timer do not function. However, timer A operates, provided that
the event counter mode is set to an external pulse, and UARTi (i = 0 to 2) functions provided an external
clock is selected. Table 1.6 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. The I flag must also be set prior to stopping for an interrupt
to cancel it. After coming out of stop mode, it is recommended that four "NOP" instructions be executed
to clear the instruction queue.
When shifting to stop mode, the main clock division select bit 0 (bit 6 at 0006
Table 1.6: Port status during stop mode
Pin
Port
CLK
OUT

1.2.8 Wait Mode

When a WAIT instruction is executed, the internal clock Φ stops and the microcomputer enters the wait
mode. In this mode, oscillation continues but the internal clock Φ and watchdog timer stop. Writing "1"
to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being
supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.7 shows
the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as internal clock Φ the clock that had been selected when the WAIT
instruction was executed.
Table 1.7: Port status during wait mode
Pin
Port
CLK
OUT
1.2.9 Status Transition Of Internal Clock Φ
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
internal clock Φ. Table 1.8 shows the operating modes corresponding to the settings of system clock
control registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock
division select bit 0 (bit 6 at address 0006
internal clock
• Division by 2 mode
The main clock is divided by 2 to obtain the internal clock Φ.
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to f , and fAD stops in stop mode, peripheral functions
1 32
Retains status before stop mode
Retains status before stop mode
Retains status before stop mode
Does not stop when the WAIT peripheral function clock stop bit is "0". When the
WAIT peripheral function clock stop bit is "1", the status immediately prior to
entering WAIT mode is maintained.
) is set to "1". The following shows the operational modes of
16
) stops all oscillation and the
16
) is set to "1".
16
Single-chip mode
Single-chip mode
Stop Mode