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Section 13 Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
Figure 13.1 shows a block diagram of the DMAC.
13.1
Features
• Four channels (Two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
(longword × 4)
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests
External request
On-chip peripheral module request
Auto request
The following modules can issue an on-chip peripheral module request.
SCIF0, SCIF1, SCIF2, MTU0, MTU1, MTU2, MTU3, MTU4, USB, CMT0, CMT1, A/D
converter 0, A/D converter 1
• Selectable bus modes
Cycle steal mode (normal mode and intermittent mode)
Burst mode
• Selectable channel priority levels: The channel priority levels are selectable between fixed
mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU at the end of the specified
counts of data transfer.
• External request detection: There are following four types of DREQ input detection.
Low level detection
High level detection
Rising edge level detection
Falling edge level detection
Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 405 of 982
REJ09B0023-0400
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