Relation Between Writing To Tdr And Tdre Flag; Restrictions On Using Dmac; Figure 12.33 Sample Transmission Using Dmac In Clocked Synchronous Mode - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

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Relation between Writing to TDR and TDRE Flag

The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from

TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.

Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written

to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR

yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the

TDRE flag is set to 1.

• When the external clock source is used as a synchronization clock, update TDR by the DMAC

and wait for at least five Pφ clock cycles before allowing the transmit clock to be input. If the

transmit clock is input within four clock cycles after TDR modification, the SCI may

malfunction (figure 12.33).

• When using the DMAC to read RDR, be sure to set the receive end interrupt (RXI) as the

DMAC activation source.

Note: When external clock is supplied, t must be more than four clock cycles.

Section 12 Serial Communication Interface (SCI)

Rev. 3.00 Mar. 14, 2006 Page 443 of 804

REJ09B0104-0300

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