Figure 16.16 Sample Sci Transmission Operation In Clocked Synchronous Mode - Renesas H8S/2437 Hardware Manual

5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and
serial transmission of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the SCI maintains the output
state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is
generated. The SCK pin is fixed high.
Figure 16.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated

Figure 16.16 Sample SCI Transmission Operation in Clocked Synchronous Mode

Transfer direction
Bit 0 Bit 1
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
1 frame
Bit 7 Bit 0 Bit 1
TXI interrupt
request generated
Rev. 1.00, 09/03, page 461 of 704
Bit 6 Bit 7
TEI interrupt request
generated