Figure 6.10 Bus Timing For 16-Bit, 3-State Access Space (Even Byte Access) - Renesas H8S/2437 Hardware Manual

16-Bit, 3-State Access Space:
Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Address bus
D15 to D8
Read
D7 to D0
Write
D15 to D8
D7 to D0
Note: n = 1 to 3

Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)

Rev. 1.00, 09/03, page 110 of 704
Bus cycle
T T
1 2
High
Valid
Undefined
T
3
Valid
Invalid