Timer Status Register (Tsr) - Renesas H8SX/1500 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.5

Timer Status Register (TSR)

TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
Bit 7
Bit Name TCFD
Initial Value 1
R/W R
Note: * Only 0 can be written to bits 5 to 0, to clear flags.
Bit Bit Name
7 TCFD

6
5 TCFU
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REJ09B0104-0300
6 5
— TCFU
1 0
R R/(W)*
Initial
value R/W Description
1 R Count Direction Flag
Status flag that shows the direction in which TCNT counts
in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is a read-only bit
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
1 R Reserved
This is a read-only bit and cannot be modified.
0 R/(W)* Underflow Flag
Status flag that indicates that a TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to phase
counting mode.
In channels 0 and 3, bit 5 is reserved. It is a read-only bit
and cannot be modified.
[Setting condition]
•
[Clearing condition]
•
4 3
TCFV TGFD
0 0
R/(W)* R/(W)*
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
When a 0 is written to TCFU after reading TCFU = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
2 1
TGFC TGFB
0 0
R/(W)* R/(W)*
0
TGFA
0
R/(W)*